Editing Clock signal (section)

== Digital circuits ==

Most [[integrated circuit]]s (ICs) of sufficient complexity use a clock signal in order to synchronize different parts of the circuit, cycling at a rate slower than the worst-case internal [[propagation delay]]s. In some cases, more than one clock cycle is required to perform a predictable action. As ICs become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. The preeminent example of such complex chips is the [[microprocessor]], the central component of modern computers, which relies on a clock from a [[crystal oscillator]]. The only exceptions are [[asynchronous circuit]]s such as [[Asynchronous Processor|asynchronous CPUs]].

A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit. This technique is often used to save power by effectively shutting down portions of a digital circuit when they are not in use, but comes at a cost of increased complexity in timing analysis.

=== Single-phase clock ===
Most modern [[synchronous circuit]]s use only a "single phase clock" – in other words, all clock signals are (effectively) transmitted on a single wire.

=== Two-phase clock ===
In [[synchronous circuit]]s, a "two-phase clock" refers to clock signals distributed on two wires, each with non-overlapping pulses. Traditionally one wire is called "phase 1" or "φ1" ([[phi]]1), the other wire carries the "phase 2" or "φ2" signal.<ref name="Two-phase">[http://www.princeton.edu/~wolf/modern-vlsi/Overheads/CHAP5-2/sld010.htm Two-phase clock] {{webarchive |url=https://web.archive.org/web/20071109090150/http://www.princeton.edu/~wolf/modern-vlsi/Overheads/CHAP5-2/sld010.htm |date=November 9, 2007 }}</ref><ref>{{citation |url=http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-phase-clock-gen.html |title=Two-phase non-overlapping clock generator |publisher=Tams-www.informatik.uni-hamburg.de |access-date=2012-01-08 |archive-url=https://web.archive.org/web/20111226073122/http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-phase-clock-gen.html |archive-date=2011-12-26 |url-status=dead }}</ref><ref>{{citation|url=http://micro.magnet.fsu.edu/primer/digitalimaging/concepts/twophase.html |title=Concepts in Digital Imaging - Two Phase CCD Clocking |publisher=Micro.magnet.fsu.edu |access-date=2012-01-08}}</ref><ref>{{citation |url=http://www.hpc.msstate.edu/mpl/distributions/scmos/scmos_doc/cells/cgf104.html |title=Cell cgf104: Two phase non-overlapping clock generator |publisher=Hpc.msstate.edu |access-date=2012-01-08 |url-status=dead |archive-url=https://web.archive.org/web/20120208054348/http://www.hpc.msstate.edu/mpl/distributions/scmos/scmos_doc/cells/cgf104.html |archive-date=2012-02-08 }}</ref>  Because the two phases are guaranteed non-overlapping, [[gated latch]]es rather than [[edge-triggered flip-flop]]s can be used to store [[State (computer science)#Digital logic circuit state|state information]] so long as the inputs to latches on one phase only depend on outputs from latches on the other phase. Since a gated latch uses only four gates versus six gates for an edge-triggered flip-flop, a two phase clock can lead to a design with a smaller overall gate count but usually at some penalty in design difficulty and performance.

[[Metal oxide semiconductor]] (MOS) ICs typically used dual clock signals (a two-phase clock) in the 1970s. These were generated externally for both the [[Motorola 6800]] and [[Intel 8080]] microprocessors.<ref name = "MC6870">{{Cite journal | title = How to drive a microprocessor | journal = Electronics | volume = 49 | issue = 8 | page =159 | publisher = McGraw-Hill | location = New York | date = April 15, 1976 | url = http://commons.wikimedia.org/wiki/File:Motorola_MC6870_ad_April_1976.jpg}} Motorola's Component Products Department sold hybrid ICs that included a quartz oscillator. These IC produced the two-phase non-overlapping waveforms the 6800 and 8080 required. Later Intel produced the 8224 clock generator and Motorola produced the MC6875. The Intel 8085 and the Motorola 6802 include this circuitry on the microprocessor chip.</ref> The next generation of microprocessors incorporated the clock generation on chip. The 8080 uses a 2&nbsp;MHz clock but the processing throughput is similar to the 1&nbsp;MHz 6800. The 8080 requires more clock cycles to execute a processor instruction. Due to their [[Dynamic logic (digital electronics)|dynamic logic]], the 6800 has a minimum clock rate of 100&nbsp;kHz and the 8080 has a minimum clock rate of 500&nbsp;kHz. Higher speed versions of both microprocessors were released by 1976.<ref name = "MD Sep 1975 8080A">{{Cite journal | title = Intel's Higher Speed 8080 μP | journal = Microcomputer Digest | volume = 2 | issue = 3 | page = 7 | publisher = Microcomputer Associates | location = Cupertino CA | date = September 1975 | url = http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n03_Sep75.pdf | access-date = 2011-01-24 | archive-date = 2019-01-23 | archive-url = https://web.archive.org/web/20190123102914/http://bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n03_Sep75.pdf | url-status = dead }}</ref>

The [[6501]] requires an external 2-phase clock generator. The [[MOS Technology 6502]] uses the same 2-phase logic internally, but also includes a 2-phase clock generator on-chip, so it only needs a single phase clock input, simplifying system design.

=== 4-phase clock ===
{{see also|Four-phase logic}}
Some early integrated circuits use [[four-phase logic]], requiring a four-phase clock input consisting of four separate, non-overlapping clock signals.<ref>{{citation |url=http://micro.magnet.fsu.edu/primer/digitalimaging/concepts/fourphase.html |title=Concepts in digital imaging - Four Phase CCD Clocking |publisher=Micro.magnet.fsu.edu |access-date=2012-01-08}}</ref> This was particularly common among early microprocessors such as the [[National Semiconductor]] [[IMP-16]], [[Texas Instruments TMS9900]], and the [[Western Digital]] [[MCP-1600]] chipset used in the [[Digital Equipment Corporation|DEC]] [[PDP-11#LSI-11|LSI-11]].

Four phase clocks have only rarely been used in newer CMOS processors such as the DEC WRL MultiTitan microprocessor.<ref>
{{cite journal |author-link=Norman P. Jouppi |last1=Jouppi |first1=N.P. |last2=Tang |first2=J.F. |title=A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance |journal=IEEE Journal of Solid-State Circuits |volume=24 |issue=5 |pages=1348–59 |date=1989 |doi=10.1109/JSSC.1989.572612 |bibcode=1989IJSSC..24.1348J |url=}}
</ref> and in [[Intrinsity]]'s Fast14 technology. Most modern microprocessors and [[microcontroller]]s use a single-phase clock.

=== Clock multiplier ===
{{main|Clock multiplier}}

Many modern [[microcomputer]]s use a "[[clock multiplier]]" which multiplies a lower frequency external clock to the appropriate [[clock rate]] of the microprocessor. This allows the CPU to operate at a much higher frequency than the rest of the computer, which affords performance gains in situations where the CPU does not need to wait on an external factor (like memory or [[input/output]]).

=== Dynamic frequency change ===

The vast majority of digital devices do not require a clock at a fixed, constant frequency. As long as the minimum and maximum clock periods are respected, the time between clock edges can vary widely from one edge to the next and back again.
Such digital devices work just as well with a clock generator that dynamically changes its frequency, such as [[spread spectrum clock|spread-spectrum clock generation]], [[dynamic frequency scaling]], etc. Devices that use [[static logic (digital logic)|static logic]] do not even have a maximum clock period (or in other words, minimum clock frequency); such devices can be slowed and paused indefinitely, then resumed at full clock speed at any later time.