Editing CompactRISC (section)

== Architectures==
Features of CR16 family: compact implementations (less than 1 mm<sup>2</sup> with [[250 nanometer|250&nbsp;nm]]), addressing of 2&nbsp;MB (2{{sup|21}}), frequencies up to 66&nbsp;MHz, hardware multiplier for 16-bit integers.<ref name=cr16-utah-beyond/>

It has complex instructions such as bit manipulation, saving/restoring and push/pop of several registers with single command.<ref name=cr16-utah-beyond/>

CR16 has 16 general purpose registers of 16 bits, and address registers of 21 bits wide. There are 8 special registers: program counter, interrupt stack pointer ISP, interrupt vector address register INTBASE, status register PSR, configuration register and 3 debug registers. Status register implements flags: C, T, L, F, Z, N, E, P, I.<ref name=cr16-utah-beyond/>

Instructions are encoded in two-address form in several formats, usually they have 16-bit encoding, but there are two formats for medium immediate instructions with length of 32-bit. Typical opcode length is 4 bits (bits 9–12 of most encoding types. Basic encoding formats are:
* Register-to-register,
* Short 5-bit immediate value to register,
* Medium immediate of 16-bit value to register (32-bit encoding),
* Load/store relative with short 5-bit displacement (2-bit opcode),
* Load/store relative with medium 18-bit displacement (32-bit encoding, 2-bit opcode).<ref name=cr16-utah-beyond/>

CR16C comes with a different opcode encoding format, has 23–32-bit-wide address registers and provides two 32-bit general purpose registers.<ref>{{cite web|url=https://dump.bitcheese.net/files/zujukix/Prog_16C.pdf|title=CR16C Programmer's Reference Manual}}</ref>

CR16 implements traps and interrupts. Implementations of CR16 has three-stage pipeline: fetch, decode, execute.<ref name=cr16-utah-beyond/>