Editing Complex programmable logic device (section)

==Features==
Some of the CPLD features are in common with [[Programmable array logic|PAL]]s:
* Non-volatile configuration memory. Unlike many FPGAs, an external configuration [[read-only memory|ROM]] is not required, and the CPLD can function immediately on system start-up.
* For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.

Other features are in common with [[field programmable gate array|FPGA]]s:
* Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of [[logic gate]]s, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
* Some provisions for logic more flexible than [[disjunctive normal form|sum-of-product]] expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly used functions, such as [[integer]] [[arithmetic]].

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for "[[boot loader]]" functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.<ref>{{cite web
 | url = http://only-vlsi.blogspot.com/2008/05/complex-programmable-logic-device.html
 | title = Complex Programmable Logic Device
 |date=May 2008 | access-date = 2013-11-17
 | publisher = blogspot.com
}}</ref>