Editing Cray X-MP (section)

==Description==
The X-MP's main improvement over the Cray-1 was that it was a shared-memory [[Parallel computing|parallel]] [[vector processor]], the first such computer from Cray Research. It housed up to four CPUs in a mainframe that was nearly identical in outside appearance to the Cray-1.

The X-MP CPU had a faster 9.5&nbsp;[[nanosecond]] clock cycle (105&nbsp;MHz), compared to 12.5&nbsp;ns for the Cray-1A. It was built from [[Bipolar junction transistor|bipolar]] [[gate-array]] [[integrated circuit]]s containing 16 [[emitter-coupled logic]] [[Logic gate|gate]]s each. The CPU was very similar to the Cray-1 CPU in architecture, but had better memory bandwidth (with two read ports and one write port to the main memory instead of only one read/write port) and improved chaining support. Each CPU had a theoretical peak performance of 200&nbsp;MFLOPS.<ref name=brochure>Cray Research, Inc. (1985). [http://archive.computerhistory.org/resources/text/Cray/Cray.X-MP.1985.102646183.pdf "The Cray X-MP Series of Computer Systems"].</ref>

The X-MP initially supported 2 million 64-bit [[Word (data type)|word]]s (16 MB) of main memory in 16 banks, respectively.{{citation needed|date=November 2015}} The main memory was built from 4&nbsp;Kbit bipolar SRAM ICs.{{citation needed|date=November 2015}} CMOS memory versions of the Cray-1M were renamed Cray X-MP/1s. This configuration was first used for Cray Research's UNIX port.

In 1984, improved models of the X-MP were announced, consisting of one, two, and four-processor systems with 4 and 8 million word configurations. The top-end system was the X-MP/48, which contained four CPUs with a theoretical peak system performance of over 800&nbsp;MFLOPS and 8 million words of memory.<ref name=brochure /> The CPUs in these models introduced vector [[Gather-scatter (vector addressing)|gather/scatter]] memory reference instructions to the product line. The amount of main memory supported was increased to a maximum of 16 million words, depending on the model. The main memory was built from bipolar or MOS SRAM ICs, depending on the model.

The system initially ran the proprietary [[Cray Operating System]] (COS) and was object-code compatible with the Cray-1. A [[UNIX System V]] derivative initially named CX-OS and finally renamed [[UNICOS]] ran through a guest [[operating system]] facility. UNICOS became the main OS from 1986 onwards. The [[United States Department of Energy|DOE]] ran the [[Cray Time Sharing System]] and the [[NLTSS]] operating systems instead. See the Software section for the [[Cray-1]] for a more detailed elaboration of software (language compiler, assembler, operating systems, and applications) as X-MPs and Cray-1s were mostly compatible.