Editing DEC Alpha (section)

==History==

===PRISM===
{{main|DEC PRISM}}
Alpha emerged from an earlier RISC project named Parallel Reduced Instruction Set Machine ([[DEC PRISM|PRISM]]), itself the product of several earlier projects. PRISM was intended to be a flexible design, supporting Unix-like applications, and Digital's existing VAX/VMS software, after minor conversion. A new [[operating system]] named [[DEC MICA|MICA]] would support both [[ULTRIX]] and VAX/VMS interfaces on a common [[Kernel (operating system)|kernel]], allowing software for both platforms to be easily ported to the PRISM architecture.<ref name="mica-business-plan">{{cite web|url=http://www.bitsavers.org/pdf/dec/prism/mica/Mica_Software_Business_Plan_Mar87.pdf|title=MICA Software Business Plan|author1=Catherine Richardson|author2=Terry Morris|author3=Rockie Morgan|author4=Reid Brown|author5=Donna Meikle|date=March 1987|access-date=2021-01-04|website=bitsavers.org|archive-date=2021-01-07|archive-url=https://web.archive.org/web/20210107155539/http://www.bitsavers.org/pdf/dec/prism/mica/Mica_Software_Business_Plan_Mar87.pdf|url-status=live}}</ref>

Started in 1985, the PRISM design was continually changed during its development in response to changes in the computer market, leading to lengthy delays in its introduction. It was not until the summer of 1987 that it was decided that it would be a [[64-bit computing|64-bit]] design, among the earliest such designs in a [[microprocessor]] format. In October 1987, [[Sun Microsystems]] introduced the [[Sun-4]], their first [[workstation]] using their new [[SPARC]] processor. The Sun-4 runs about three to four times as fast as their latest [[Sun-3]] designs using the [[Motorola 68020]], and any Unix offering from DEC. The plans changed again; PRISM was realigned once again as a 32-bit part and aimed directly at the Unix market. This further delayed the design.<ref name="microprism">{{cite web |first= Bob |last= Supnik |url= http://simh.trailing-edge.com/semi/uprism.html |title= MicroPrism |date= 24 February 2008 |website= The Computer History Simulation Project |access-date= 26 April 2021 |archive-date= 3 April 2021 |archive-url= https://web.archive.org/web/20210403101425/http://simh.trailing-edge.com/semi/uprism.html |url-status= live}}</ref>

Having watched the PRISM delivery date continue to slip, and facing the possibility of more delays, a team in the Palo Alto office decided to design their own workstation using another RISC processor. After [[due diligence]], they selected the [[R2000 (microprocessor)|MIPS R2000]] and built a working workstation running Ultrix in a period of 90 days.<ref>{{cite web |url=http://alasir.com/articles/alpha_history/prism_to_alpha.html |title=Alpha: The History in Facts and Comments |access-date=2019-09-09 |date=2007-04-22 |first=Paul V |last=Bolotoff |archive-date=2019-09-29 |archive-url=https://web.archive.org/web/20190929230557/http://alasir.com/articles/alpha_history/prism_to_alpha.html |url-status=live}}</ref> This sparked off an acrimonious debate within the company, which came to a head in a July 1988 management meeting. PRISM appeared to be faster than the R2000, but the R2000 machines could be in the market by January 1989, a year earlier than PRISM. When this proposal was accepted, one of the two original roles for PRISM disappeared. The decision to make a VMS PRISM had already ended by this point, so there was no remaining role. PRISM was cancelled at the meeting.<ref>{{cite web |title=Sketch of DEC PRISM |author=Mark Smotherman |url=https://people.cs.clemson.edu/~mark/prism.html |quote=PRISM (Parallel Reduced Instruction Set Machine) ... first draft of PRISM architecture in August 1985; DEC cancels the project in 1988 in favor of a MIPS-based ... |access-date=2018-09-20 |archive-date=2020-04-04 |archive-url=https://web.archive.org/web/20200404100105/https://people.cs.clemson.edu/~mark/prism.html |url-status=live}}</ref>

===RISCy VAX===
As the meeting broke up, Bob Supnik was approached by [[Ken Olsen]], who stated that the RISC chips appeared to be a future threat to their VAX line. He asked Supnik to consider what might be done with VAX to keep it competitive with future RISC systems.<ref name="microprism"/>

This led to the formation of the "RISCy VAX" team. They initially considered three concepts. One was a cut-down version of the VAX [[instruction set architecture]] (ISA) that would run on a RISC-like system and leave more complex VAX instructions to system subroutines. Another concept was a pure RISC system that would translate existing VAX code into its own ISA on-the-fly and store it in a [[CPU cache]]. Finally, there was still the possibility of a much faster CISC processor running the complete VAX ISA. Unfortunately, all of these approaches introduced overhead and would not be competitive with a pure-RISC machine running native RISC code.<ref name="comerford">{{cite journal |first=Richard |last=Comerford |title=How DEC developed Alpha |journal=[[IEEE Spectrum]] |volume=29 |issue=7 |date=July 1992 |page=28 |doi=10.1109/6.144508 |url=https://ieeexplore.ieee.org/document/144508 |access-date=2021-10-23 |archive-date=2018-06-20 |archive-url=https://web.archive.org/web/20180620235313/https://ieeexplore.ieee.org/document/144508/ |url-status=live}}</ref>

The group then considered hybrid systems that combined one of their existing VAX one-chip solution and a RISC chip as a coprocessor used for high-performance needs. These studies suggested that the system would inevitably be hamstrung by the lower-performance part and would offer no compelling advantage. It was at this point that Nancy Kronenberg pointed out that people ran VMS, not VAX, and that VMS only had a few hardware dependencies based on its modelling of [[interrupt]]s and memory paging. There appeared to be no compelling reason why VMS could not be ported to a RISC chip as long as these small bits of the model were preserved. Further work on this concept suggested this was a workable approach.<ref name="comerford"/>

Supnik took the resulting report to the Strategy Task Force in February 1989. Two questions were raised: could the resulting RISC design also be a performance leader in the Unix market, and should the machine be an open standard? And with that, the decision was made to adopt the PRISM architecture with the appropriate modifications. This became the "EVAX" concept, a follow-on to the successful CMOS [[CVAX]] implementation. When management accepted the findings, they decided to give the project a more neutral name, removing "VAX", eventually settling on Alpha.<ref>{{cite journal |url=https://www.hpl.hp.com/hpjournal/dtj/vol4num4/foreword.htm |title=Foreword |first=Bob |last=Supnik |journal=Digital Technical Journal |volume=4 |issue=4 |date=1992 |access-date=2021-05-03 |archive-date=2021-05-03 |archive-url=https://web.archive.org/web/20210503222246/https://www.hpl.hp.com/hpjournal/dtj/vol4num4/foreword.htm |url-status=live}}</ref> The name was inspired by the use of "Omega" as the codename of an [[NVAX]]-based [[VAX 4000]] model; "Alpha" was intended to signify the beginning of a new line (with reference to [[Alpha and Omega]]).<ref>{{cite interview |last=Supnik|first=Robert|interviewer=Gardner Hendrie|title=Robert Supnik Oral History|url=https://archive.computerhistory.org/resources/access/text/2019/07/102738263-05-01-acc.pdf |publisher=Computer History Museum|date=2017-05-02|website=computerhistory.org|access-date=2024-04-06}}</ref> Soon after, work began on [[OpenVMS#Port to Alpha|a port of VMS to the new architecture]].<ref>{{cite web|url=https://dspace.mit.edu/bitstream/handle/1721.1/48380/managingtechnolo00katz.pdf|date=April 1993|title=Managing Technological Leaps: A study of DEC's Alpha Design Team|access-date=2021-04-26|archive-date=2021-02-07|archive-url=https://web.archive.org/web/20210207063545/https://dspace.mit.edu/bitstream/handle/1721.1/48380/managingtechnolo00katz.pdf|url-status=live}}</ref>

===Alpha===
The new design uses most of the basic PRISM concepts, but was re-tuned to allow VMS and VMS programs to run at reasonable speed with no conversion at all. The primary Alpha instruction set architects were Richard L. Sites and Richard T. Witek.<ref>{{cite book |url=https://www.elsevier.com/books/alpha-axp-architecture-reference-manual/sites/978-1-4831-8403-6 |isbn=978-1-4831-8403-6 |title=Alpha AXP Architecture Reference Manual – 2nd Edition |author1=Richard L. Sites |author2=Richard T. Witek |date=2014-05-16 |publisher=Digital Press |access-date=2018-09-20 |archive-date=2018-09-20 |archive-url=https://web.archive.org/web/20180920122621/https://www.elsevier.com/books/alpha-axp-architecture-reference-manual/sites/978-1-4831-8403-6 |url-status=live}}</ref> The PRISM's Epicode was developed into the Alpha's [[PALcode]], providing an abstracted interface to platform- and processor implementation-specific features.

The main contribution of Alpha to the microprocessor industry, and the main reason for its performance, is not so much the architecture but rather its implementation.<ref>{{Cite web|url=https://www.ibm.com/developerworks/library/pa-microhist/|title=Great moments in microprocessor history|last=Warner|first=W.|date=December 22, 2004|website=IBM|access-date=January 18, 2018|archive-date=January 19, 2018|archive-url=https://web.archive.org/web/20180119120058/https://www.ibm.com/developerworks/library/pa-microhist/|url-status=live}}</ref> At that time (as it is now), the microchip industry was dominated by automated design and layout tools. The chip designers at Digital continued pursuing sophisticated manual circuit design in order to deal with the complex VAX architecture. The Alpha chips show that manual circuit design applied to a simpler, cleaner architecture allows for much higher operating frequencies than those that are possible with the more automated design systems. These chips caused a renaissance of custom circuit design within the microprocessor design community.

Originally, the Alpha processors were designated the ''DECchip 21x64'' series,<ref name=X21>{{cite web
|title=cpu-collection.de – DEC Alpha AXP
|url=http://www.cpu-collection.de/?l0=co&l1=DEC&l2=Alpha+AXP
|quote=The first processors of the Alpha family were designated the DECchip 21064 series (the "21" signifying 21st century)
|access-date=2018-09-20
|archive-date=2018-09-20
|archive-url=https://web.archive.org/web/20180920160836/http://www.cpu-collection.de/?l0=co&l1=DEC&l2=Alpha+AXP
|url-status=live
}}</ref> with "DECchip" replaced in the mid-1990s with "Alpha". The first two digits, "21" signifies the 21st century, and the last two digits, "64" signifies 64 bits.<ref name=X21/> The Alpha was designed as 64-bit from the start and there is no 32-bit version. The middle digit corresponds to the generation of the Alpha architecture. Internally, Alpha processors were also identified by ''EV'' numbers, EV officially standing for "Extended VAX" but having an alternative humorous meaning of "Electric [[Vlasic Pickles|Vlasic]]", giving homage to the [[Glowing pickle demonstration|Electric Pickle]] experiment at Western Research Lab.<ref name=pickle>{{cite journal
  | title = WRL Technical Note TN-13: Characterization of Organic Illumination Systems
  | publisher = Digital Equipment Corporation
  | year = 1989
  | url = https://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-13.html
  | format = [[PDF]]
  | access-date = 2007-10-04
  | author1 = Bill Hamburgen
  | author2 = Jeff Mogul
  | author3 = Brian Reid
  | author-link3 = Brian Reid (computer scientist)
  | author4 = Alan Eustace
  | author-link4 = Alan Eustace
  | author5 = Richard Swan
  | author6 = Mary Jo Doherty
  | author7 = Joel Bartlett
  | journal = 
  | archive-date = 2008-05-12
  | archive-url = https://web.archive.org/web/20080512033558/http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-13.html
  | url-status = dead
  }}</ref> The number in the EV designations indicated the semiconductor process which the chip was designed for. For example, the EV4 processor used DEC's CMOS-4 process.<ref name="comerford" />

In May 1997, DEC sued [[Intel]] for allegedly infringing on its Alpha patents in designing the [[Original Intel Pentium (P5 microarchitecture)|original Pentium]], [[Pentium Pro]], and [[Pentium II]] chips.<ref>{{cite magazine|title=DEC, Cyrix sue Intel|first1=Gale|last1=Bradley|first2=Jim|last2=DeTar|magazine=Electronic News|volume=43|issue=2168|pages=1, 60|date=May 19, 1997|issn=1061-6624|url=https://archive.org/details/sim_electronic-news_1997-05-19_43_2168/mode/1up}}</ref> As part of a settlement, much of DEC's chip design and fabrication business was sold to Intel. This included DEC's [[StrongARM]] implementation of the [[ARM architecture family|ARM computer architecture]], which Intel marketed as the [[Intel XScale|XScale]] processors commonly used in [[Pocket PC]]s. The core of Digital Semiconductor, the Alpha microprocessor group, remained with DEC, while the associated office buildings went to Intel as part of the Hudson fab.<ref>{{cite interview |first=Allan |last=Baum |interviewer= David Brock |title=Oral History of Allen Baum |date=July 18, 2018 |url=https://archive.computerhistory.org/resources/access/text/2018/06/102717165-05-01-acc.pdf |archive-url=https://web.archive.org/web/20210207063355/https://archive.computerhistory.org/resources/access/text/2018/06/102717165-05-01-acc.pdf |archive-date=2021-02-07 |url-status=live |page=60}}</ref>

===Improved models===
The first few generations of the Alpha chips were some of the most innovative of their time.
* A pre-production model, designated ''EV3'', was used in a prototype system named the ''Alpha Demonstration Unit'' (ADU). ADUs were used to port operating systems to the Alpha architecture. One key difference between the EV3 and later models was the absence of a floating-point unit.<ref>{{cite journal|url=https://vmssoftware.com/docs/dtj-v04-04-1992.pdf|title=The Alpha Demonstration Unit: A High-performance Multiprocessor for Software and Chip Development|author1=Charles P. Thacker|author2=David G. Conroy|author3=Lawrence C. Stewart|journal=Digital Technical Journal|volume=4|issue=4|year=1992|access-date=2024-04-06|page=51}}</ref>
* The first version, the ''[[Alpha 21064]]'' or ''EV4'', is the first [[CMOS]] microprocessor whose operating frequency rivalled higher-powered [[Emitter coupled logic|ECL]] minicomputers and mainframes. 
* The second, ''21164'' or ''EV5'', is the first microprocessor to place a large secondary cache on-chip.<ref>{{cite journal |title=Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor |author1=John H. Edmondson |author2=Paul I. Rubinfeld |author3=Peter J. Bannon |author4=Bradley J. Benschneider |author5=Debra Bernstein |author6=Ruben W. Castelino |author7=Elizabeth M. Cooper |author8=Daniel E. Dever |author9=Dale R. Donchin |author10=Timothy C. Fischer |author11=Anil K. Jain |author12=Shekhar Mehta |author13=Jeanne E. Meyer |author14=Ronald P. Preston |author15=Vidya Rajagopalan |author16=Chandrasekhara Somanathan |author17=Scott A. Taylor |author18=Gilbert M. Wolrich |journal=Digital Technical Journal |volume=7 |issue=1 |year=1995 |pages=119–135 |quote=large, on-chip, second-level, write-back cache |citeseerx=10.1.1.38.9551}}</ref>
* The third, ''21264'' or ''EV6'', is the first microprocessor to combine both high operating frequency and the more complicated [[out-of-order execution]] microarchitecture. 
* The ''21364'' or ''EV7'' is the first high performance processor to have an on-chip [[memory controller]].<ref>{{cite book
|quote=21364 ... first high performance processor to have an onchip memory controller.
|title=Structured Computer Organization
|url=https://books.google.com/books?isbn=147842673X
|isbn=978-1478426738 |date=2016|last1=Reviews
|first1=C.T.I
}}</ref> 
* The unproduced ''[[Alpha 21464|21464]]'' or ''EV8'' would have been the first to include [[simultaneous multithreading]], but this version was canceled after the sale of DEC to [[Compaq]]. The ''[[Alpha 21464#Tarantula|Tarantula]]'' research project, which most likely would have been called ''EV9'', would have been the first Alpha processor to feature a [[vector processor]] unit.<ref name='Tarantula'>{{cite conference
  | author1 = Roger Espasa
  | author2 = Federico Ardanaz
  | author3 = Julio Gago
  | author4 = Roger Gramunt
  | author5 = Isaac Hernandez
  | author6 = Toni Juan
  | author7 = Joel Emer
  | author7-link = Joel Emer
  | author8 = Stephen Felix
  | author9 = Geoff Lowney
  | author10 = Matthew Mattina
  | author11 = Andre Seznec
  | year = 2002
  | editor = Danielle C. Martin
  | others = Joe Daigle/Studio Productions
  | title = Tarantula: A Vector Extension to the Alpha Architecture
  | url = http://systems.cs.colorado.edu/ISCA2002/
  | conference = 29th Annual International Symposium on Computer Architecture (ISCA '02)
  | conference-url = http://systems.cs.colorado.edu/ISCA2002
  | book-title = Proceedings: 29th Annual International Symposium on Computer Architecture (ISCA '02)
  | pages = 281–292
  | publisher = IEEE Computer Society
  | location = Los Alamitos, Calif
  | isbn = 0-7695-1605-X
  | doi = 10.1109/ISCA.2002.1003586
  | url-status = live
  | archive-url = https://web.archive.org/web/20071004172421/http://systems.cs.colorado.edu/ISCA2002/
  | archive-date = 2007-10-04
  | access-date = 2007-10-04
}}</ref>

A persistent report attributed to DEC insiders suggests the choice of the ''AXP'' tag for the processor was made by DEC's legal department, which was still smarting from the [[Vax (brand)#Trademark conflict|VAX trademark]] fiasco.<ref>{{cite web |title=The VAX Vacuum 
|url=https://groups.google.com/d/topic/comp.os.vms/8ptFdR3KYxg
|quote=... legally, if DEC had used VAX in the U.S. before that ..... "reasonable person" has no difficulty distinguishing between the two uses}}</ref> After a lengthy search the tag "AXP" was found to be entirely unencumbered. Within the computer industry, a joke got started that the acronym ''AXP'' meant "Almost eXactly PRISM".<ref>{{Cite mailing list |mailing-list=Linux kernel mailing list |author=Chad Page |title=The meaning of AXP (was Re: ALPHA ambiguity) |date=30 April 1996 |url=https://lkml.org/lkml/1996/5/1/47 |access-date=2024-08-29}}</ref>