Editing DLX (section)

==History==
In the Stanford MIPS architecture, one of the methods used to gain performance was to force all instructions to complete in one clock cycle. This forced compilers to insert "[[NOP (code)|no-ops]]" in cases where the instruction would definitely take longer than one clock cycle. Thus input and output activities (like memory accesses) specifically forced this behaviour, leading to artificial program bloat. In general, MIPS programs were forced to have a lot of wasteful NOP instructions, a behaviour that was an unintended consequence. The DLX architecture does not force single clock cycle execution, and is therefore immune to this problem.

In the DLX design, a more modern approach to handling long instructions was used: data-forwarding and instruction reordering. In this case, the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they can complete. Externally, this design behaviour makes it appear as if execution had occurred linearly.