Editing Design rule checking (section)

==Design rules==
[[Image:The three basic DRC checks.svg|300px|right|thumb|The basic DRC checks - width, spacing, and enclosure]]

Design rules are a series of parameters provided by [[Semiconductor fabrication|semiconductor manufacturer]]s that enable the designer to verify the correctness of a [[mask set]]. Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly.

The most basic design rules are shown in the diagram on the right. The first are single layer rules. A ''width'' rule specifies the minimum width of any shape in the design. A ''spacing'' rule specifies the minimum distance between two adjacent objects. These rules will exist for each layer of semiconductor manufacturing process, with the lowest layers having the smallest rules (typically 100&nbsp;nm as of 2007) and the highest metal layers having larger rules (perhaps 400&nbsp;nm as of 2007).

A two layer rule specifies a relationship that must exist between two layers. For example, an ''enclosure'' rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer. A typical value as of 2007 might be about 10&nbsp;nm.

There are many other rule types not illustrated here. A ''minimum area'' rule is just what the name implies. [[Antenna effect|Antenna rules]] are complex rules that check ratios of areas of every layer of a net for configurations that can result in problems when intermediate layers are etched.<ref>{{Cite web |title=Antenna Effect Simulation & Application |url=https://scholar.google.com/citations?view_op=view_citation&hl=en&user=GXghZfgAAAAJ&sortby=pubdate&citation_for_view=GXghZfgAAAAJ:mnAcAzq93VMC |access-date=2024-02-26 |website=scholar.google.com}}</ref> Many other such rules exist and are explained in detail in the documentation provided by the semiconductor manufacturer.

Academic design rules are often specified in terms of a scalable parameter, '''λ''', so that all geometric tolerances in a design may be defined as integer multiples of '''λ'''. This simplifies the migration of existing chip layouts to newer processes. Industrial rules are more highly optimized, and only approximate uniform scaling. Design rule sets have become increasingly more complex with each subsequent generation of semiconductor process.<ref>{{cite web | url=https://semiengineering.com/design-rule-complexity-rising/ | title=Design Rule Complexity Rising | date=19 April 2018 }}</ref>