Editing Double data rate (section)

==Overview==
The simplest way to design a clocked [[electronic circuit]] is to make it perform one transfer per full cycle (rise and fall) of a [[clock signal]].  This, however, requires that the clock signal changes twice per transfer, while the data lines change at most once per transfer.  When operating at a high bandwidth, [[signal integrity]] limitations constrain the clock [[frequency]].{{citation needed|date=May 2021}}  By using both edges of the clock, the data signals operate with the same limiting frequency, thereby doubling the data transmission rate.

This technique has been used for microprocessor [[front-side bus]]ses, [[Parallel SCSI#Ultra-3|Ultra-3 SCSI]], expansion buses ([[Accelerated Graphics Port|AGP]], [[PCI-X]]<ref>{{cite web |last1=Schmid |first1=Patrick |title=PCI Express Battles PCI-X |url=https://www.tomshardware.com/reviews/pci-express-battles-pci,1176-2.html |website=Tom's Hardware Guide|date=23 November 2005 }}</ref>), graphics memory ([[GDDR]]), [[SDRAM|main memory]] (both [[RDRAM]] and [[DDR SDRAM|DDR1]] through [[DDR5]]), and the [[HyperTransport]] bus on [[AMD]]'s [[Athlon 64]] processors. It is more recently being used for other systems with high data transfer speed requirements{{spaced ndash}} as an example, for the output of [[analog-to-digital converter]]s (ADCs).<ref>{{cite web |title= AD9467 ADC | type = data sheet |url= http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf |publisher= Analog Devices}}</ref>

DDR should not be confused with [[Dual-channel architecture|dual channel]], in which each memory channel accesses two RAM modules simultaneously. The two technologies are independent of each other and many motherboards use both, by using DDR memory in a dual channel configuration.

An alternative to double or [[Quad data rate|quad pumping]] is to make the link [[self-clocking]]. This tactic was chosen by [[InfiniBand]] and [[PCI Express]].