Editing Emitter-coupled logic (section)

== History ==
[[Image:CurrentSwitchLogic.svg|350px|thumb|right|Yourke's current switch (around 1955)<ref name="Rymaszewski"/>]]

ECL was invented in August 1956 at [[IBM]] by Hannon S. Yourke.<ref>[http://semiconductormuseum.com/Transistors/IBM/OralHistories/Yourke/Yourke_Index.htm Early Transistor History at IBM].</ref><ref>{{Citation |url=http://archive.computerhistory.org/resources/text/IBM/Stretch/pdfs/06-11/102634289.pdf |title=Millimicrosecond non-saturating transistor switching circuits |first=Hannon S. |last=Yourke |id=Stretch Circuit Memo # 3 |date=October 1956 }}. Yourke's circuits used commercial transistors and had an average gate delay of 12&nbsp;ns.</ref> Originally called ''current-steering logic'', it was used in the [[IBM 7030 Stretch|Stretch]], [[IBM 7090]], and [[IBM 7090#IBM 7094 and IBM 7040/7044|IBM 7094]] computers.<ref name="Rymaszewski">{{cite journal |author=E. J. Rymaszewski |year=1981 |title=Semiconductor Logic Technology in IBM |journal=IBM Journal of Research and Development |volume=25 |issue=5 |pages=607–608 |issn=0018-8646 |url=http://researchweb.watson.ibm.com/journal/rd/255/ibmrd2505W.pdf |access-date=August 27, 2007 |doi=10.1147/rd.255.0603 |display-authors=etal |url-status=dead |archive-url=https://web.archive.org/web/20080705164759/http://researchweb.watson.ibm.com/journal/rd/255/ibmrd2505W.pdf |archive-date=July 5, 2008 }}</ref>  The logic was also called a current-mode circuit.<ref>{{cite book |title=High-Speed Switching Transistor Handbook |editor-first=William D. |editor-last=Roehr |editor2-first=Darrell |editor2-last=Thorpe |year=1963 |publisher=Motorola |url=https://archive.org/details/High-speedSwitchingHandbook }}, p. 37.</ref>  It was also used to make the IBM Advanced [[Solid Logic Technology]] (ASLT) circuits in the IBM 360/91.<ref>{{cite book |title=IBM's 360 and Early 370 Systems |page=108 |date=2003 |isbn=0262517205|last1=Pugh |first1=Emerson W. |last2=Johnson |first2=Lyle R. |last3=Palmer |first3=John H. |publisher=MIT Press }}</ref><ref name="ASLT">{{cite journal |year=1967 |title=Design of a High-Speed Transistor for the ASLT Current Switch |journal=IBM Journal of Research and Development |first1=J.L. |last1=Langdon |first2=E.J. |last2=VanDerveer |volume=11 |pages=69–73 |url=http://www.research.ibm.com/journal/rd/111/ibmrd1101G.pdf |doi=10.1147/rd.111.0069 }}</ref><ref name=Blocks>{{cite web|title=Logic Blocks Automated Logic Diagrams SLT, SLD, ASLT, MST |url=http://bitsavers.trailing-edge.com/pdf/ibm/logic/SY22-2798-2_LogicBlocks_AutomatedLogicDiagrams_SLT,SLD,ASLT,MST_TO_Oct71.pdf|publisher=IBM|access-date=September 11, 2015|pages=1–10 |via=Bitsavers}}</ref>

Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level."<ref>{{Harvnb|Roehr|Thorpe|1963|p=39}}</ref> In Yourke's design, the two logic reference levels differed by 3&nbsp;volts.<!-- This would keep the collector to base capacitance small and improve switching speed. Roehr page 40 advises keeping a minimum Vcb of at least 2V -- that's a typical design goal to minimize effect of Ccb, but Roehr does not actually state it is for Ccb. --> Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."<ref name="Rymaszewski"/>

Instead of alternating NPN and PNP stages, another coupling method employed [[Zener diode]]s and resistors to shift the output logic levels to be the same as the input logic levels.<ref>{{Harvnb|Roehr|Thorpe|1963|pp=40, 261}}</ref>

Beginning in the early 1960s, ECL circuits were implemented on [[monolithic integrated circuit]]s. They consisted of a differential-amplifier input stage to perform logic followed by an emitter-follower stage to drive outputs and shift the output voltages so they will be compatible with the inputs. The emitter-follower output stages could also be used to perform [[Wired logic connection|wired-or logic]].

{{anchor|MECL}}[[Motorola]] introduced their first digital monolithic integrated circuit line, MECL I, in 1962.<ref>{{cite book |first=William R. |last=Blood Jr. |date=1988 |orig-year=1980 |url=http://www.onsemi.com/pub/Collateral/HB205-D.PDF |title=MECL System Design Handbook |edition=4th |publisher=Motorola Semiconductor Products, republished by On Semiconductor|page=vi |archive-url=https://web.archive.org/web/20041010110305/http://www.onsemi.com/pub/Collateral/HB205-D.PDF |archive-date=October 10, 2004}}</ref> Motorola developed several improved series, with MECL II in 1966, MECL III in 1968 with 1-nanosecond gate propagation time and 300&nbsp;MHz flip-flop toggle rates, and the 10,000 series (with lower power consumption and controlled edge speeds) in 1971.<ref>{{cite book |first=William R. |last=Blood Jr. |title=MECL System Design Handbook |edition=1st |date=October 1971 |publisher=Motorola  |pages=vi–vii |url=http://www.bitsavers.org/components/motorola/_dataBooks/1971_Motorola_MECL_System_Design_Handbook_1ed_Oct71.pdf |via=Bitsavers}}</ref>
The MECL 10H family was introduced in 1981.<ref name="TND309">{{cite book
|url=http://www.onsemi.com/pub_link/Collateral/TND309-D.PDF |title=TND309: General Information for MECL 10H and MECL 10K
|date=2002 |publisher=ON Semiconductor: Semiconductor Components Industries |id=TND309/D
|page=2
|archive-url=https://web.archive.org/web/20150708060625/http://www.onsemi.com/pub_link/Collateral/TND309-D.PDF |archive-date=July 8, 2015
}}</ref>
Fairchild introduced the F100K family in 1975.<ref>{{cite journal |last1=Hively |first1=J. W. |last2=Muller |first2=H. H. |last3=Owens |first3=W. K. |title=F100K, A Standard Family of Subnanosecond ECL |journal=Fairchild Journal of Semiconductor Progress |volume=3 |issue=3 |pages=16-21 |url=https://www.computerhistory.org/collections/catalog/102798005 |access-date=30 October 2024}}</ref><ref>{{cite web |title=Thomas A. Longo: Department of Physics and Astronomy: Purdue University |url=https://www.physics.purdue.edu/alumni/distalum/longo.html |website=www.physics.purdue.edu}}</ref>

The ECLinPS ("ECL in picoseconds") family was introduced in 1987.<ref>{{cite book |first=Anil K. |last=Maini |url=https://books.google.com/books?id=Ljsr7UA83ScC |title=Digital Electronics: Principles, Devices and Applications
|date=2007 |page=148|publisher=John Wiley & Sons |isbn=9780470510513 }}</ref> ECLinPS has 500 ps single-gate delay and 1.1&nbsp;GHz flip-flop toggle frequency.<ref>{{Cite FTP |url=ftp://ece.buap.mx/pub/manuales/High%20Performace%20ECL%20Data.pdf |title=High Performance ECL Data: ECLinPS and ECLinPS Lite |date=1996 |server=FTP server |url-status=dead |page=iii }}</ref> The ECLinPS family parts are available from multiple sources, including Arizona Microtek, Micrel (subsequently acquired by Microchip Technology Inc.), National Semiconductor, and ON Semiconductor.<ref>
[http://www.interfacebus.com/ECL_Logic_Manufacturers.html ECL Logic Manufacturers – "Emitter Coupled Logic"].
</ref>

The high power consumption of ECL meant that it has been used mainly when high speed is a vital requirement. Older high-end mainframe computers, such as the [[IBM ES/9000 family|Enterprise System/9000]] members of IBM's [[ESA/390]] computer family, used ECL,<ref name=barish/> as did the [[Cray-1]],<ref name="Russell">{{cite journal |first=R.M. |last=Russell |year=1978 |title=The CRAY1 computer system|journal=Communications of the ACM |volume=21 |issue=1 |pages=63–72 |url=http://www.eecg.toronto.edu/~moshovos/ACA05/read/cray1.pdf
|access-date=April 27, 2010 |doi=10.1145/359327.359336 |s2cid=28752186 }}</ref> and first-generation [[Amdahl Corporation|Amdahl]] mainframes. (Current IBM mainframes use [[CMOS]].<ref>{{cite web|url=http://www.redbooks.ibm.com/redpieces/pdfs/sg248050.pdf |title=IBM zEnterprise System Technical Introduction |date=August 1, 2013 |url-status=dead |archive-url=https://web.archive.org/web/20131103060023/http://www.redbooks.ibm.com/redpieces/pdfs/sg248050.pdf |archive-date=November 3, 2013 }}</ref>) Beginning in 1975, [[Digital Equipment Corporation]]'s highest performance processors were all based on multi-chip ECL CPUs—from the ECL [[PDP-10|KL10]] through the ECL [[VAX 8000]] and finally the [[VAX 9000]]. By 1991, the CMOS [[NVAX]] was launched, which offered comparable performance to the VAX 9000 despite costing 1/25 as much and consuming considerably less power.<ref>
{{cite web |first=Bob |last=Supnik 
|url=http://simh.trailing-edge.com/semi/raven.html |title=Raven: Introduction: The ECL Conundrum |quote=Raven was started in 1988... Raven was a simplified VAX design with a single chip CPU and a single chip FPU. Implemented in Fujitsu's ECL standard cells, it was intended to run at 250Mhz and deliver 50 "VUPS" ... Power dissipation would have been a startling (for the day) 150W. }}
</ref> The [[R6000|MIPS R6000]] computers also used ECL. Some of these computer designs used ECL [[gate array]]s.