Editing Explicitly parallel instruction computing (section)

==Roots in VLIW==
By 1989, researchers at HP recognized that [[reduced instruction set computer]] (RISC) architectures were reaching a limit at one [[instruction per cycle]].{{Clarify|date=September 2009}} They began an investigation into a new architecture, later named '''EPIC'''.<ref name="HP_Labs"/> The basis for the research was [[Very long instruction word|VLIW]], in which multiple operations are encoded in every instruction, and then processed by multiple execution units.

One goal of EPIC was to move the complexity of instruction scheduling from the CPU hardware to the software [[compiler]], which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal was to further exploit [[instruction-level parallelism]] (''ILP'') by using the compiler to find and exploit additional opportunities for [[parallel computing|parallel execution]].

''VLIW'' (at least the original forms) has several short-comings that precluded it from becoming mainstream:
* VLIW [[instruction set]]s are not [[backward compatibility|backward compatible]] between implementations. When [[wide-issue|wider]] implementations (more [[execution unit]]s) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
* Load responses from a [[memory hierarchy]] which includes [[CPU cache]]s and [[DRAM]] do not have a deterministic delay.{{why|date=March 2024}} This makes static scheduling of load instructions by the compiler very difficult.
EPIC architecture evolved from VLIW architecture, but retained many concepts of the [[superscalar]] architecture.