Editing Fault model (section)

==Basic fault models==
Basic '''fault models''' in [[digital circuit]]s include:
*Static faults, which give incorrect values at any speed and sensitized by performing only one operation:
** the [[stuck-at fault]] model.  A signal, or gate output, is stuck at a 0 or 1 value, independent of the inputs to the circuit.
** the [[bridging fault]] model.  Two signals are connected together when they should not be.  Depending on the logic circuitry employed, this may result in a ''wired-OR'' or ''wired-AND'' logic function.  Since there are ''O(n^2)'' potential bridging faults, they are normally restricted to signals that are physically adjacent in the design.
** the [[transistor fault]]s. This model is used to describe faults for CMOS logic gates. At transistor level, a transistor maybe stuck-short or stuck-open. In stuck-short, a transistor behaves as it is always conducts (or stuck-on), and stuck-open is when a transistor never conducts current (or stuck-off). Stuck-short will produce a short between VDD and VSS.
** The [[open fault]] model.  Here a wire is assumed broken, and one or more inputs are disconnected from the output that should drive them.  As with bridging faults, the resulting behavior depends on the circuit implementation.
*Dynamic faults, only at-speed and are sensitized by performing multiple operations sequentially:
** The transition [[delay fault]] (or transition fault) model, where the signal eventually assumes the correct value, but more slowly (or rarely, more quickly) than normal.
** Small-delay-defect model  <ref>[https://www.edn.com/small-delay-defect-testing-2/ "Small-delay-defect testing"]</ref> <ref>[https://pdfs.semanticscholar.org/48dd/046555cdb964fdec370906e921dbc2d4fcf8.pdf "OPTIMIZING TEST PATTERN GENERATION USING TOP-OFF ATPG"]</ref>