Editing Fin field-effect transistor (section)

==History==
The concept of a [[double-gate]] [[thin-film transistor]] (TFT) was proposed by H. R. Farrah ([[Bendix Corporation]]) and R. F. Steinberg in 1967.<ref name="FarrahSteinberg">{{cite journal |first1=H. R. |last1=Farrah |first2=R. F. |last2=Steinberg |title=Analysis of double-gate thin-film transistor | journal=IEEE Transactions on Electron Devices |date=February 1967 |volume=14 |issue=2 |pages=69–74 |doi=10.1109/T-ED.1967.15901 |bibcode=1967ITED...14...69F}}</ref> A double-gate MOSFET was later proposed by Toshihiro Sekigawa of the [[Electrotechnical Laboratory]] (ETL) in a 1980 [[patent]] describing the planar [[XMOS]] transistor.<ref name="Koike">{{cite journal |first1=Hanpei |last1=Koike |first2=Tadashi |last2=Nakagawa |first3=Toshiro |last3=Sekigawa |first4=E. |last4=Suzuki |first5=Toshiyuki |last5=Tsutsumi |s2cid=189033174 |title=Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode |journal=TechConnect Briefs |date=23 February 2003 |volume=2 |issue=2003 |pages=330–333 }}</ref> Sekigawa fabricated the XMOS transistor with Yutaka Hayashi at the ETL in 1984. They demonstrated that [[short-channel effect]]s can be significantly reduced by sandwiching a fully depleted [[silicon-on-insulator]] (SOI) device between two [[gate electrode]]s connected together.<ref name="Colinge">{{cite book |last1=Colinge |first1=J. P. |title=FinFETs and Other Multi-Gate Transistors |date=2008 |publisher=Springer Science & Business Media |isbn=9780387717517 |pages=11 & 39 |url=https://books.google.com/books?id=t1ojkCdTGEEC&pg=PA11}}</ref><ref>{{cite journal |last1=Sekigawa |first1=Toshihiro |last2=Hayashi |first2=Yutaka |title=Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate |journal=Solid-State Electronics |date=August 1984 |volume=27 |issue=8 |pages=827–828 |doi=10.1016/0038-1101(84)90036-4 |bibcode=1984SSEle..27..827S |issn=0038-1101}}</ref>

The first FinFET transistor type was called a "Depleted Lean-channel Transistor" (DELTA) transistor, which was first fabricated in Japan by [[Hitachi|Hitachi Central Research Laboratory]]'s Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.<ref name="Colinge"/><ref>{{cite book |last1=Hisamoto |first1=Digh |last2=Kaga |first2=Toru |last3=Kawamoto |first3=Yoshifumi |last4=Takeda |first4=Eiji |title=International Technical Digest on Electron Devices Meeting |chapter=A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET |date=December 1989 |pages=833–836 |doi=10.1109/IEDM.1989.74182|s2cid=114072236 }}</ref><ref>{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-url=https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html |url-status=dead |archive-date=September 9, 2018 |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref> The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a ''tri-gate transistor'' and the latter a ''double-gate transistor''. A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is called ''split transistor,'' enabling more refined control of the operation of the transistor.

Indonesian engineer Effendi Leobandung, while working at the [[University of Minnesota]], published a paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of cutting a wide [[CMOS]] transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width.<ref name="Leobandung">{{cite book |last1=Leobandung |first1=Effendi |last2=Chou |first2=Stephen Y. |title=1996 54th Annual Device Research Conference Digest |chapter=Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length |date=1996 |pages=110–111 |doi=10.1109/DRC.1996.546334|isbn=0-7803-3358-6 |s2cid=30066882 }}</ref> This structure is what a modern FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins.<ref>{{cite thesis |last1=Leobandung |first1=Effendi |title=Nanoscale MOSFETs and single charge transistors on SOI |date=June 1996 |publisher=University of Minnesota |type=Ph.D. thesis |location=Minneapolis, Minnesota |page=72}}</ref><ref>{{Cite journal |last1=Leobandung |first1=Effendi |last2=Gu |first2=Jian |last3=Guo |first3=Lingjie |last4=Chou |first4=Stephen Y. |date=1997-11-01 |title=Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects |url=http://dx.doi.org/10.1116/1.589729 |journal=Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena |volume=15 |issue=6 |pages=2791–2794 |doi=10.1116/1.589729 |bibcode=1997JVSTB..15.2791L |issn=1071-1023|url-access=subscription }}</ref> The device had a [[32 nanometer|35&nbsp;nm]] channel width and [[65-nanometer process|70&nbsp;nm]] channel length.<ref name="Leobandung"/>

The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the [[DARPA|Defense Advanced Research Projects Agency]] (DARPA), which in 1997 awarded a contract to a research group at the [[University of California, Berkeley]] to develop a deep [[Nanoelectronics|sub-micron]] transistor based on DELTA technology.<ref name="intel">{{cite web |title=The Breakthrough Advantage for FPGAs with Tri-Gate Technology |url=https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01201-fpga-tri-gate-technology.pdf |publisher=[[Intel]] |year=2014 |access-date=4 July 2019}}</ref> The group was led by Hisamoto along with [[TSMC]]'s [[Chenming Hu]]. The team made the following breakthroughs between 1998 and 2004.<ref name="Liu">{{cite web |last1=Tsu-Jae King |first1=Liu |author-link1=Tsu-Jae King Liu |title=FinFET: History, Fundamentals and Future |url=https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse |website=[[University of California, Berkeley]] |publisher=Symposium on VLSI Technology Short Course |date=June 11, 2012 |access-date=9 July 2019 |archive-url=https://web.archive.org/web/20160528220227/http://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse |archive-date=28 May 2016 |url-status=live }}</ref>

*1998 {{ndash}} [[N-channel]] FinFET ([[22 nm process|17&nbsp;nm]]) {{ndash}} Digh Hisamoto, Chenming Hu, [[Tsu-Jae King Liu]], Jeffrey Bokor, Wen-Chin Lee, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Kazuya Asano<ref>{{cite book |last1=Hisamoto |first1=Digh |last2=Hu |first2=Chenming |last3=Liu |first3=Tsu-Jae King |last4=Bokor |first4=Jeffrey |last5=Lee |first5=Wen-Chin |last6=Kedzierski |first6=Jakub |last7=Anderson |first7=Erik |last8=Takeuchi |first8=Hideki |last9=Asano |first9=Kazuya |title=International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) |chapter=A folded-channel MOSFET for deep-sub-tenth micron era |date=December 1998 |pages=1032–1034 |doi=10.1109/IEDM.1998.746531|isbn=0-7803-4774-9 |s2cid=37774589 }}</ref>
*1999 {{ndash}} [[P-channel]] FinFET ([[45 nanometer|sub-50&nbsp;nm]]) {{ndash}} Digh Hisamoto, Chenming Hu, Xuejue Huang, Wen-Chin Lee, Charles Kuo, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi<ref>{{cite book |last1=Hisamoto |first1=Digh |last2=Kedzierski |first2=Jakub |last3=Anderson |first3=Erik |last4=Takeuchi |first4=Hideki |title=International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) |chapter=Sub 50-nm FinFET: PMOS |date=December 1999 |pages=67–70 |doi=10.1109/IEDM.1999.823848 |chapter-url=https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet3.pdf |isbn=0-7803-5410-9 |s2cid=7310589 |access-date=2019-09-25 |archive-date=2010-06-06 |archive-url=https://web.archive.org/web/20100606054224/http://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet3.pdf |url-status=dead }}</ref>
*2001 {{ndash}} [[14 nm process|15&nbsp;nm]] FinFET {{ndash}} Chenming Hu, Yang-Kyu Choi, Nick Lindert, P. Xuan, S. Tang, D. Ha, Erik Anderson, Tsu-Jae King Liu, Jeffrey Bokor<ref>{{cite book |last1=Hu |first1=Chenming |author1-link=Chenming Hu |last2=Choi |first2=Yang-Kyu |last3=Lindert |first3=N. |last4=Xuan |first4=P. |last5=Tang |first5=S. |last6=Ha |first6=D. |last7=Anderson |first7=E. |last8=Bokor |first8=J. |last9=Tsu-Jae King |first9=Liu |title=International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) |chapter=Sub-20 nm CMOS FinFET technologies |date=December 2001 |pages=19.1.1–19.1.4 |doi=10.1109/IEDM.2001.979526|isbn=0-7803-7050-3 |s2cid=8908553 }}</ref>
*2002 {{ndash}} [[10 nm process|10&nbsp;nm]] FinFET {{ndash}} Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor, David Kyser, Chenming Hu, Tsu-Jae King Liu, Bin Yu, Leland Chang<ref>{{cite book |last1=Ahmed |first1=Shibly |last2=Bell |first2=Scott |last3=Tabery |first3=Cyrus |last4=Bokor |first4=Jeffrey |last5=Kyser |first5=David |last6=Hu |first6=Chenming |last7=Liu |first7=Tsu-Jae King |last8=Yu |first8=Bin |last9=Chang |first9=Leland |title=Digest. International Electron Devices Meeting |chapter=FinFET scaling to 10 nm gate length |date=December 2002 |pages=251–254 |doi=10.1109/IEDM.2002.1175825 |citeseerx=10.1.1.136.3757 |chapter-url=https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf |isbn=0-7803-7462-2 |s2cid=7106946 |access-date=2019-09-25 |archive-date=2020-05-27 |archive-url=https://web.archive.org/web/20200527205136/https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf |url-status=dead }}</ref>
*2004 {{ndash}} [[High-κ]]/[[metal gate]] FinFET {{ndash}} D. Ha, Hideki Takeuchi, Yang-Kyu Choi, Tsu-Jae King Liu, W. Bai, D.-L. Kwong, A. Agarwal, M. Ameen

They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper,<ref>{{cite journal |last1=Hisamoto |first1=Digh |first2=Chenming |author-link2=Chenming Hu |last2=Hu |last3=Bokor |first3=J. |first4=Tsu-Jae |last4=King |last5=Anderson |first5=E. |last6=Kuo |first6=Charles |last7=Asano |first7=K. |last8=Takeuchi |first8=H. |last9=Kedzierski |first9=J. |first10=Wen-Chin |last10=Lee |display-authors=5 |title=FinFET—a self-aligned double-gate MOSFET scalable to 20&nbsp;nm|journal=IEEE Transactions on Electron Devices|date=December 2000 |volume=47 |issue=12 |pages=2320–2325 |doi=10.1109/16.887014 |citeseerx=10.1.1.211.204 |bibcode=2000ITED...47.2320H }}</ref> used to describe a non-planar, double-gate transistor built on an SOI substrate.<ref>{{cite journal|first1=Digh|last1=Hisamoto|first2=Chenming|last2=Hu|author-link2=Chenming Hu|first3=Xuejue|last3=Huang|first4=Wen-Chin |last4=Lee|first5=Charles|last5=Kuo|first6=Leland|last6=Chang|first7=J.|last7=Kedzierski|first8=E.|last8=Anderson|first9=H.|last9=Takeuchi|first10=Yang-Kyu |last10=Choi|first11=K.|last11=Asano|first12=V.|last12=Subramanian|first13=Tsu-Jae |last13=King|first14=J.|last14=Bokor |display-authors=5 |title=Sub-50 nm P-channel FinFET |journal=IEEE Transactions on Electron Devices |date=May 2001 |volume=48 |issue=5 |pages=880–886 |doi=10.1109/16.918235|url=https://people.eecs.berkeley.edu/~hu/PUBLICATIONS/PAPERS/717.pdf|bibcode=2001ITED...48..880H}}</ref>

In 2006, a team of Korean researchers from the [[KAIST|Korea Advanced Institute of Science and Technology]] (KAIST) and the National Nano Fab Center developed a [[3&nbsp;nm]] transistor, the world's smallest [[nanoelectronic]] device, based on [[gate-all-around]] (GAA) FinFET technology.<ref>{{citation|url=http://www.highbeam.com/doc/1G1-145838158.html|archive-url=https://web.archive.org/web/20121106011401/http://www.highbeam.com/doc/1G1-145838158.html|url-status=dead|archive-date=6 November 2012|title=Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )|date=1 April 2006|work=Nanoparticle News|access-date=6 July 2019}}</ref><ref>{{Cite book|first=Hyunjin |last=Lee |title=2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers |chapter=Sub-5nm All-Around Gate FinFET for Ultimate Scaling |year=2006 |pages=58–59 |doi=10.1109/VLSIT.2006.1705215 |display-authors=etal|isbn=978-1-4244-0005-8 |hdl=10203/698 |s2cid=26482358 |hdl-access=free }}</ref> In 2011, [[Rice University]] researchers Masoud Rostami and Kartik Mohanram demonstrated that FinFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.<ref>{{cite journal|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |volume=30 |issue=3 |pages=337–349 |doi=10.1109/TCAD.2010.2097310 |year=2011 |last1=Rostami |first1=M. |last2=Mohanram |first2=K. |title=Dual-V<sub>th</sub> Independent-Gate FinFETs for Low Power Logic Circuits |hdl=1911/72088 |s2cid=2225579 |url=https://scholarship.rice.edu/bitstream/1911/72088/1/Masoud%20Journal.pdf |hdl-access=free }}</ref>

In 2020, Chenming Hu received the [[IEEE Medal of Honor]] award for his development of the FinFET, which the [[Institute of Electrical and Electronics Engineers]] (IEEE) credited with taking transistors to the third dimension and extending [[Moore's law]].<ref>{{cite news |title=How the Father of FinFETs Helped Save Moore's Law: Chenming Hu, the 2020 IEEE Medal of Honor recipient, took transistors into the third dimension |url=https://spectrum.ieee.org/how-the-father-of-finfets-helped-save-moores-law |access-date=27 December 2021 |work=[[IEEE Spectrum]] |date=21 April 2020 |language=en}}</ref>