Editing Flash memory (section)

==History==
===Background===
The origins of flash memory can be traced to the development of the [[Floating-gate MOSFET|floating-gate MOSFET (FGMOS)]], also known as the floating-gate transistor.<ref name="economist">{{Cite news |date=11 March 2006 |title=Not just a flash in the pan |agency=[[Reuters]] |url=https://www.economist.com/technology-quarterly/2006/03/11/not-just-a-flash-in-the-pan |url-status=live |url-access=limited |access-date=10 September 2019 |archive-url=https://web.archive.org/web/20231121163825/https://www.economist.com/technology-quarterly/2006/03/11/not-just-a-flash-in-the-pan |archive-date=21 November 2023 |newspaper=[[The Economist]] }}</ref><ref name="Bez">{{cite book |last1=Bez |first1=R. |last2=Pirovano |first2=A. |title=Advances in Non-Volatile Memory and Storage Technology |date=2019 |publisher=[[Woodhead Publishing]] |isbn=9780081025857}}</ref> The original [[MOSFET]] was invented at Bell Labs between 1955 and 1960, after Frosch and Derick discovered surface passivation and used their discovery to create the first planar transistors.<ref>{{Cite patent|number=US2802760A|title=Oxidation of semiconductive surfaces for controlled diffusion|gdate=1957-08-13|invent1=Lincoln|invent2=Frosch|inventor1-first=Derick|inventor2-first=Carl J.|url=https://patents.google.com/patent/US2802760A}}</ref><ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref><ref>{{Cite journal |last=KAHNG |first=D. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories|pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5 |url-access=subscription }}</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref><ref>{{Cite journal |last1=Ligenza |first1=J.R. |last2=Spitzer |first2=W.G. |date=1960 |title=The mechanisms for silicon oxidation in steam and oxygen |url=https://linkinghub.elsevier.com/retrieve/pii/0022369760902195 |journal=Journal of Physics and Chemistry of Solids |language=en |volume=14 |pages=131–136 |doi=10.1016/0022-3697(60)90219-5|bibcode=1960JPCS...14..131L |url-access=subscription }}</ref><ref name="Lojek12022">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=120}}</ref> [[Dawon Kahng]] went on to develop a variation, the floating-gate MOSFET, with Taiwanese-American engineer [[Simon Min Sze]] at Bell Labs in 1967.<ref name="computerhistory1971">{{Cite web |date=11 June 2018 |title=1971: Reusable semiconductor ROM introduced |url=https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/ |url-status=live |archive-url=https://web.archive.org/web/20230810204956/https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/ |archive-date=10 August 2023 |access-date=19 June 2019 |website=The Storage Engine |publisher=[[Computer History Museum]] }}</ref> They proposed that it could be used as floating-gate [[memory cell (computing)|memory cells]] for storing a form of programmable [[read-only memory]] ([[Programmable read-only memory|PROM]]) that is both non-volatile and re-programmable.<ref name="computerhistory1971"/>

Early types of floating-gate memory included EPROM (erasable PROM) and EEPROM (electrically erasable PROM) in the 1970s.<ref name="computerhistory1971" /> However, early floating-gate memory required engineers to build a memory cell for each [[bit]] of data, which proved to be cumbersome,<ref name="forbes">{{cite web |last=Fulford |first=Adel |title=Unsung hero |work=Forbes |date=24 June 2002 |access-date=18 March 2008 |url=https://www.forbes.com/global/2002/0624/030.html |url-status=live |archive-url=https://web.archive.org/web/20080303205125/http://www.forbes.com/global/2002/0624/030.html |archive-date=3 March 2008}}</ref> slow,<ref name="howstuffworks-rom">{{Cite web |last=Tyson |first=Jeff |date=29 August 2000 |title=How ROM Works |url=https://computer.howstuffworks.com/rom.htm#pt5 |url-status=live |archive-url=https://web.archive.org/web/20231202082951/https://computer.howstuffworks.com/rom.htm#pt5 |archive-date=2 December 2023 |access-date=10 September 2019 |website=[[HowStuffWorks]] }}</ref> and expensive, restricting floating-gate memory to niche applications in the 1970s, such as [[military equipment]] and the earliest experimental [[mobile phones]].<ref name="economist" />

===Invention and commercialization===
Modern [[EEPROM]] based on [[Field electron emission#Fowler–Nordheim tunneling|Fowler-Nordheim tunnelling]] to erase data was invented by Bernward and patented by [[Siemens]] in 1974.<ref>{{Cite patent|number=GB1517925A|title=Storage field effect transistors|gdate=1978-07-19|url=https://patents.google.com/patent/GB1517925A/en}}</ref> It was further developed between 1976 and 1978 by [[Eli Harari|Eliyahou Harari]] at [[Hughes Aircraft Company]], as well as by [[George Perlegos]] and others at Intel.<ref>{{cite web |last1=Simko |first1=Richard T. |date=17 March 1977 |title=Electrically programmable and electrically erasable MOS memory cell |url=https://patents.google.com/patent/US4119995A/en}}</ref><ref>{{cite web |last1=Frohman-Bentchkowsky |first1=Dov |last2=Mar |first2=Jerry |last3=Perlegos |first3=George |last4=Johnson |first4=William S. |date=15 December 1978 |title=Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same |url=https://patents.google.com/patent/US4203158A/en}}</ref> This led to Masuoka's invention of flash memory at Toshiba in 1980.<ref name="forbes"/><ref>{{patent|US|4531203|Fujio Masuoka}}</ref><ref>{{US patent|4531203|Semiconductor memory device and method for manufacturing the same}}</ref> The improvement between EEPROM and flash being that flash is programmed in blocks while EEPROM is programmed in bytes. According to Toshiba, the name "flash" was suggested by Masuoka's colleague, Shōji Ariizumi, because the erasure process of the memory contents reminded him of the [[flash (photography)|flash of a camera]].<ref>{{cite web |url=http://www.eweek.com/c/a/Data-Storage/NAND-Flash-Memory-25-Years-of-Invention-Development-684048/ |archive-url=https://archive.today/20140818204913/http://www.eweek.com/c/a/Data-Storage/NAND-Flash-Memory-25-Years-of-Invention-Development-684048/ |url-status=dead |archive-date=18 August 2014 |title=NAND Flash Memory: 25 Years of Invention, Development – Data Storage – News & Reviews  |work=eWeek.com |access-date=18 August 2014 }}</ref> Masuoka and colleagues presented the invention of [[#NOR memories|NOR]] flash in 1984,<ref name="auto1">{{Cite web |title=Toshiba: Inventor of Flash Memory |url=http://www.flash25.toshiba.com |url-status=dead |archive-url=https://web.archive.org/web/20190620160642/http://www.flash25.toshiba.com/ |archive-date=20 June 2019 |access-date=20 June 2019 |website=[[Toshiba]] }}</ref><ref name="ieee-1984">{{Cite conference |last2=Asano |first2=M. |last3=Iwahashi |first3=H. |last4=Komuro |first4=T. |last5=Tanaka |first5=S. |date=December 1984 |title=A new flash E<sup>2</sup>PROM cell using triple polysilicon technology |conference=1984 [[International Electron Devices Meeting]] |location=San Francisco|pages=464–467 |doi=10.1109/IEDM.1984.190752 |s2cid=25967023 |first1=F. |last1=Masuoka }}</ref> and then [[#NAND memories|NAND]] flash at the ''[[Institute of Electrical and Electronics Engineers|IEEE]] 1987 International Electron Devices Meeting'' (IEDM) held in San Francisco.<ref>{{cite conference |title=New ultra high density EPROM and flash EEPROM with NAND structure cell |last1=Masuoka |first1=F. |last2=Momodomi |first2=M. |last3=Iwata |first3=Y. |last4=Shirota |first4=R. |year=1987 |pages=552–555 |conference=[[International Electron Devices Meeting|IEDM]] 1987 |book-title=Electron Devices Meeting, 1987 International |publisher=[[IEEE]]|doi=10.1109/IEDM.1987.191485}}</ref>

Toshiba commercially launched NAND flash memory in 1987.<ref name=":0">{{cite web |title=1987: Toshiba Launches NAND Flash |url=https://www.eweek.com/storage/1987-toshiba-launches-nand-flash |website=[[eWeek]] |date=11 April 2012 |access-date=20 June 2019}}</ref><ref name="computerhistory1971"/> [[Intel Corporation]] introduced the first commercial NOR type flash chip in 1988.<ref>{{cite web |url=http://www2.electronicproducts.com/NAND_vs_NOR_flash_technology-article-FEBMSY1-FEB2002.aspx |title=NAND vs. NOR flash technology: The designer should weigh the options when using flash memory |last=Tal |first=Arie |date=February 2002 |access-date=31 July 2010 |url-status=dead |archive-url=https://web.archive.org/web/20100728210327/http://www2.electronicproducts.com/NAND_vs_NOR_flash_technology-article-FEBMSY1-FEB2002.aspx |archive-date=28 July 2010}}</ref> NOR-based flash has long erase and write times, but provides full address and [[data bus]]es, allowing [[random access]] to any [[memory location]]. This makes it a suitable replacement for older [[read-only memory]] (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computer's [[BIOS]] or the [[firmware]] of [[set-top box]]es. Its endurance may be from as little as 100 erase cycles for an on-chip flash memory,<ref name="rej09b0138_h8s2357.pdf">{{Cite web |date=October 2004 |title=H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398F-ZTATTM Hardware Manual |url=https://www.renesas.com/us/en/document/mas/h8s2357-group-h8s2357f-ztattm-h8s2398f-ztattm-hardware-manual |url-status=live |archive-url=https://web.archive.org/web/20230109212444/https://www.renesas.com/us/en/document/mas/h8s2357-group-h8s2357f-ztattm-h8s2398f-ztattm-hardware-manual |archive-date=9 January 2023 |access-date=23 January 2012 |publisher=[[Renesas Electronics|Renesas]] |page=574 |quote=The flash memory can be reprogrammed up to 100 times. }}</ref> to a more typical 10,000 or 100,000 erase cycles, up to 1,000,000 erase cycles.<ref name="amd-22271A">{{Cite web |date=July 2003 |title=AMD DL160 and DL320 Series Flash: New Densities, New Features |url=http://www.spansion.com/Support/Application%20Notes/AMD%20DL160%20and%20DL320%20Series%20Flash-%20New%20Densities,%20New%20Features.pdf |url-status=dead |archive-url=https://web.archive.org/web/20150924104223/http://www.spansion.com/Support/Application%20Notes/AMD%20DL160%20and%20DL320%20Series%20Flash-%20New%20Densities,%20New%20Features.pdf |archive-date=24 September 2015 |access-date=13 November 2014 |publisher=[[AMD]] |id=22271A |quote=The devices offer single-power-supply operation (2.7 V to 3.6 V), sector architecture, Embedded Algorithms, high performance, and a 1,000,000 program/erase cycle endurance guarantee. }}</ref> NOR-based flash was the basis of early flash-based removable media; [[CompactFlash]] was originally based on it, although later cards moved to less expensive NAND&nbsp;flash.

NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR&nbsp;flash. However, the I/O interface of NAND&nbsp;flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This makes NAND&nbsp;flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers require byte-level random access. In this regard, NAND&nbsp;flash is similar to other secondary [[data storage device]]s, such as hard disks and [[optical media]], and is thus highly suitable for use in mass-storage devices, such as [[memory card]]s and [[solid-state drive]]s (SSD). For example, SSDs store data using multiple NAND flash memory chips.

The first NAND-based removable memory card format was [[SmartMedia]], released in 1995. Many others followed, including [[MultiMediaCard]], [[Secure Digital]], [[Memory Stick]], and [[xD-Picture Card]].

===Later developments===
A new generation of memory card formats, including [[RS-MMC]], [[miniSD]] and [[microSD]], feature extremely small form factors. For example, the microSD card has an area of just over 1.5&nbsp;cm<sup>2</sup>, with a thickness of less than 1&nbsp;mm.

NAND flash has achieved significant levels of memory [[Transistor density|density]] as a result of several major technologies that were commercialized during the late 2000s to early 2010s.<ref name="James">{{Cite conference |date=May 2014 |title=3D ICs in the real world |url=https://www.researchgate.net/publication/271453642 |conference=25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014) |location=Saratoga Springs, NY |pages=113–119 |doi=10.1109/ASMC.2014.6846988 |isbn=978-1-4799-3944-2 |issn=2376-6697 |doi-access= |last1=James |first1=Dick |s2cid=42565898 |url-access=subscription }}</ref>

NOR flash was the most common type of Flash memory sold until 2005, when NAND flash overtook NOR flash in sales.<ref>{{Cite web|url=https://www.cnet.com/culture/nand-overtakes-nor-in-flash-memory/|title=NAND overtakes NOR in flash memory|website=CNET}}</ref>

[[Multi-level cell]] (MLC) technology stores more than one [[bit]] in each [[memory cell (computing)|memory cell]]. [[NEC]] demonstrated [[multi-level cell]] (MLC) technology in 1998, with an 80{{nbsp}}[[Mebibit|Mb]] flash memory chip storing 2 bits per cell.<ref name="nec-97-10-28-01">{{Cite press release |last=Bridgman |first=Aston |date=28 October 1997 |title=NEC and SanDisk Develop 80Mb Flash Memory |url=http://www.nec.co.jp/press/en/9710/2801.html |url-status=dead |archive-url=https://web.archive.org/web/20201018114043/http://www.nec.co.jp/press/en/9710/2801.html |archive-date=18 October 2020 |publisher=[[NEC]] |id=97/10/28-01 }}</ref> [[STMicroelectronics]] also demonstrated MLC in 2000, with a 64{{nbsp}}MB [[NOR flash]] memory chip.<ref name="stol"/> In 2009, Toshiba and [[SanDisk]] introduced NAND flash chips with QLC technology storing 4 bits per cell and holding a capacity of 64{{nbsp}}Gb.<ref name="toshiba2009"/><ref name="toshiba-sd-2009"/> [[Samsung Electronics]] introduced [[triple-level cell]] (TLC) technology storing 3-bits per cell, and began mass-producing NAND chips with TLC technology in 2010.<ref name="samsung-history"/>

====Charge trap flash====
{{Main|Charge trap flash}}

[[Charge trap flash]] (CTF) technology replaces the polysilicon floating gate, which is sandwiched between a blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer; the silicon nitride layer traps electrons. In theory, CTF is less prone to electron leakage, providing improved data retention.<ref name="electronicdesign-20130415">{{Cite news |last=Wong |first=Bill |date=15 April 2013 |title=Interview: Spansion's CTO Talks About Embedded Charge Trap NOR Flash Technology |work=Electronic Design |url=https://www.electronicdesign.com/technologies/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |url-status=live |archive-url=https://web.archive.org/web/20231204125719/https://www.electronicdesign.com/technologies/embedded/digital-ics/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |archive-date=4 December 2023 }}</ref><ref name="ito-taito-2017">{{Cite book |last1=Ito |first1=Takashi |title=Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations  |last2=Taito |first2=Yasuhiko |date=9 September 2017 |publisher=[[Springer Publishing]] |isbn=978-3-319-55306-1 |editor-last=Hidaka |editor-first=Hideto |series=Integrated Circuits and Systems |pages=209–244 |chapter=SONOS Split-Gate eFlash Memory |doi=10.1007/978-3-319-55306-1_7 }}</ref><ref name="ieee-91-4">{{Cite journal |last1=Bez |first1=Roberto |last2=Camerlenghi |first2=E. |last3=Modelli |first3=Alberto |last4=Visconti |first4=Angelo |date=April 2003 |title=Introduction to flash memory |journal=[[Proceedings of the IEEE]] |publisher=[[Institute of Electrical and Electronics Engineers]] |volume=91 |issue=4 |pages=498–502 |doi=10.1109/JPROC.2003.811702 }}</ref><ref name="lee-2011">{{Cite journal |last=Lee |first=Jang-Sik |date=18 October 2011 |title=Review paper: Nano-floating gate memory devices |journal=Electronic Materials Letters |publisher=Korean Institute of Metals and Materials |volume=7 |issue=3 |pages=175–183 |doi=10.1007/s13391-011-0901-5 |bibcode=2011EML.....7..175L |s2cid=110503864 }}</ref><ref name="auto5">{{Cite web |last=Aravindan |first=Avinash |date=13 November 2018 |title=Flash 101: Types of NAND Flash |url=https://www.embedded.com/flash-101-types-of-nand-flash/ |url-status=live |archive-url=https://web.archive.org/web/20231106101540/https://www.embedded.com/flash-101-types-of-nand-flash/ |archive-date=6 November 2023 |website=embedded.com }}</ref><ref name="nanoscale-9-1-526">{{Cite journal |last1=Meena |first1=Jagan Singh |last2=Sze |first2=Simon Min |last3=Chand |first3=Umesh |last4=Tseng |first4=Tseung-Yuen |date=25 September 2014 |title=Overview of emerging nonvolatile memory technologies |journal=Nanoscale Research Letters |volume=9 |issue=1 |page=526 |doi=10.1186/1556-276x-9-526 |issn=1556-276X |id=526 |doi-access=free |pmid=25278820 |pmc=4182445 |bibcode=2014NRL.....9..526M }}</ref>

Because CTF replaces the polysilicon with an electrically insulating nitride, it allows for smaller cells and higher endurance (lower degradation or wear). However, electrons can become trapped and accumulate in the nitride, leading to degradation. Leakage is exacerbated at high temperatures since electrons become more excited with increasing temperatures. CTF technology, however, still uses a tunneling oxide and blocking layer, which are the weak points of the technology, since they can still be damaged in the usual ways (the tunnel oxide can be degraded due to extremely high electric fields and the blocking layer due to Anode Hot Hole Injection (AHHI).<ref name="techtarget-20230619">{{Cite web |last=Sheldon |first=Robert |date=19 June 2023 |title=Charge trap technology advantages for 3D NAND flash drives |url=https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |url-status=live |archive-url=https://web.archive.org/web/20230809223937/https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |archive-date=9 August 2023 |website=SearchStorage }}</ref><ref name="grossi-zambelli-olivo-2016">{{Cite book |last1=Grossi |first1=A. |title=3D Flash Memories |last2=Zambelli |first2=C. |last3=Olivo |first3=P. |date=7 June 2016 |publisher=[[Springer Science+Business Media]] |isbn=978-94-017-7512-0 |editor-last=Micheloni |editor-first=Rino |location=Dordrecht |pages=29–62 |chapter=Reliability of 3D NAND Flash Memories |doi=10.1007/978-94-017-7512-0_2 }}</ref>

Degradation or wear of the oxides is the reason why flash memory has limited endurance. Data retention goes down (the potential for data loss increases) with increasing degradation, since the oxides lose their electrically-insulating characteristics as they degrade. The oxides must insulate against electrons to prevent them from leaking, which would cause data loss.

In 1991, [[NEC]] researchers, including N. Kodama, K. Oyama and Hiroki Shirai, described a type of flash memory with a charge-trap method.<ref name="iedm-1991-symmetrical">{{Cite conference |last1=Kodama |first1=N. |last2=Oyama |first2=K. |last3=Shirai |first3=H. |last4=Saitoh |first4=K. |last5=Okazawa |first5=T. |last6=Hokari |first6=Y. |date=December 1991 |title=A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory |conference=[[International Electron Devices Meeting]] |location=Washington, DC  |publisher=[[Institute of Electrical and Electronics Engineers|IEEE]] |pages=303–306 |doi=10.1109/IEDM.1991.235443 |isbn=0-7803-0243-5 |issn=0163-1918 |s2cid=111203629 }}</ref> In 1998, Boaz Eitan of [[Saifun Semiconductors]] (later acquired by [[Spansion]]) [[patented]] a flash memory technology named NROM that took advantage of a charge trapping layer to replace the conventional [[floating gate]] used in conventional flash memory designs.<ref>{{cite web|last=Eitan|first=Boaz|title=US Patent 5,768,192: Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping|url=http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5,768,192.PN.&OS=PN/5,768,192&RS=PN/5,768,192|publisher=US Patent & Trademark Office|access-date=22 May 2012|archive-date=22 February 2020|archive-url=https://web.archive.org/web/20200222215754/http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5%2C768%2C192.PN.&OS=PN%2F5%2C768%2C192&RS=PN%2F5%2C768%2C192|url-status=dead}}</ref> In 2000, an [[Advanced Micro Devices]] (AMD) research team led by Richard M. Fastow, Egyptian engineer Khaled Z. Ahmed and Jordanian engineer Sameer Haddad (who later joined Spansion) demonstrated a charge-trapping mechanism for NOR flash memory cells.<ref name="ieee-letters-21-4">{{Cite journal |last1=Fastow |first1=Richard M. |last2=Ahmed |first2=Khaled Z. |last3=Haddad |first3=Sameer |last4=Randolph |first4=Mark |last5=Huster |first5=C. |last6=Hom |first6=P. |date=April 2000 |title=Bake induced charge gain in NOR flash cells |url=https://www.researchgate.net/publication/3253902 |journal=[[IEEE Electron Device Letters]] |volume=21 |issue=4 |pages=184–186 |bibcode=2000IEDL...21..184F |doi=10.1109/55.830976 |issn=1558-0563 |s2cid=24724751 }}</ref> CTF was later commercialized by AMD and [[Fujitsu]] in 2002.<ref name="auto3">{{Cite news |last=Hruska |first=Joel |date=6 August 2013 |title=Samsung produces first 3D NAND, aims to boost densities, drive lower cost per GB |work=[[ExtremeTech]] |url=https://www.extremetech.com/computing/163221-samsung-produces-first-3d-nand-aims-to-boost-densities-drive-lower-cost-per-gb |url-status=live |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20231102133725/https://www.extremetech.com/computing/163221-samsung-produces-first-3d-nand-aims-to-boost-densities-drive-lower-cost-per-gb |archive-date=2 November 2023 }}</ref> 3D [[V-NAND]] (vertical NAND) technology stacks NAND flash memory cells vertically within a chip using 3D charge trap flash (CTP) technology. 3D V-NAND technology was first announced by Toshiba in 2007,<ref name="toshiba-3d"/> and the first device, with 24 layers, was commercialized by [[Samsung Electronics]] in 2013.<ref name="samsung-3d"/><ref name="samsung-3d-ee"/>

====3D integrated circuit technology====

[[3D integrated circuit]] (3D IC) technology stacks [[integrated circuit]] (IC) chips vertically into a single 3D IC package.<ref name="James"/> Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16{{nbsp}}[[Gibibyte|GB]] eMMC compliant (product number THGAM0G7D8DBAI6, often abbreviated THGAM on consumer websites) embedded NAND flash memory package, which was manufactured with eight stacked 2{{nbsp}}GB NAND flash chips.<ref name="toshiba2007"/> In September 2007, [[Hynix Semiconductor]] (now [[SK Hynix]]) introduced 24-layer 3D IC technology, with a 16{{nbsp}}GB flash memory package that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.<ref name="hynix2007"/> Toshiba also used an eight-layer 3D IC for their 32{{nbsp}}GB THGBM flash package and in 2008.<ref name="toshiba2008"/> In 2010, Toshiba used a 16-layer 3D IC for their 128{{nbsp}}GB THGBM2 flash package, which was manufactured with 16 stacked 8{{nbsp}}GB chips.<ref name="toshiba2010"/> In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in [[mobile devices]].<ref name="James"/>

In 2016, Micron and Intel introduced a technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking,<ref>{{Cite web|url=https://www.theregister.com/2018/08/06/china_aims_to_build_dramspeed_flash/|title=NAND we'll send foreign tech packing, says China of Xtacking: DRAM-speed... but light on layer-stacking|first=Chris|last=Mellor|website=www.theregister.com}}</ref> in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or sections a flash memory chip has, increasing from two planes to four, without increasing the area dedicated to the control or periphery circuitry. This increases the number of IO operations per flash chip or die, but it also introduces challenges when building capacitors for charge pumps used to write to the flash memory.<ref name="auto8">{{Cite web|url=https://www.anandtech.com/show/16491/flash-memory-at-isscc-2021|title=2021 NAND Flash Updates from ISSCC: The Leaning Towers of TLC and QLC|first=Billy|last=Tallis|website=www.anandtech.com}}</ref><ref>{{Cite news|url=https://www.theregister.com/2018/11/05/sk_hynix_96_layer_flash_chip/|title=What the PUC: SK Hynix next to join big boys in 96-layer 3D NAND land|first=Chris|last=Mellor|website=www.theregister.com}}</ref><ref>{{Cite news|url=https://www.theregister.com/2016/02/22/microns_journey_into_the_depths_of_nonvolatility/|title=Look who's avoided getting chatty about XPoint again. Micron... let's get non-volatile|first=Chris|last=Mellor|website=www.theregister.com}}</ref> Some flash dies have as many as 6 planes.<ref>{{Cite web |last=Alcorn |first=Paul |date=2022-07-26 |title=Micron Takes Lead With 232-Layer NAND Flash, up to 2TB per Chip Package |url=https://www.tomshardware.com/news/micron-takes-lead-with-232-layer-nand-up-to-2tb-per-chip-package |access-date=2024-05-31 |website=Tom's Hardware |language=en}}</ref>

As of August 2017, microSD cards with a capacity up to 400 [[gigabyte|GB]] (400 billion bytes) were available.<ref name="sandisk-20170831">{{Cite press release |date=31 August 2017 |title=Western Digital Breaks Boundaries with World's Highest-Capacity microSD Card |url=https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |url-status=dead |archive-url=https://web.archive.org/web/20170901035345/https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |archive-date=1 September 2017 |access-date=2 September 2017 |publisher=[[SanDisk]] |place=Berlin }}</ref><ref name="forbes-20170831">{{Cite magazine |last=Bradley |first=Tony |date=31 August 2017 |title=Expand Your Mobile Storage With New 400GB microSD Card From SanDisk |url=https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk |url-status=live |magazine=[[Forbes]] |archive-url=https://web.archive.org/web/20170901064146/https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk/ |archive-date=1 September 2017 |access-date=2 September 2017 }}</ref> Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512{{nbsp}}GB KLUFG8R1EM flash memory package with eight stacked 64-layer V-NAND chips.<ref name="anandtech-20171205" /> In 2019, Samsung produced a 1024{{nbsp}}[[Gigabyte|GB]] flash package, with eight stacked 96-layer V-NAND package and with QLC technology.<ref name="electronicsweekly-samsung"/><ref name="anandtech-samsung-2018"/>

In 2025, researchers announced experimental success with a device a 400-picosecond write time.<ref>{{Cite web |last=Shaikh |first=Kaif |title=China scientists develop flash memory 10,000× faster than current tech |url=https://interestingengineering.com/innovation/china-worlds-fastest-flash-memory-device?group=test_b |access-date=2025-04-20 |website=Interesting Engineering |language=en}}</ref>