Editing Formal equivalence checking (section)

== Equivalence checking and levels of abstraction ==

In general, there is a wide range of possible definitions of functional equivalence covering comparisons between different levels of abstraction and varying granularity of timing details. 
*The most common approach is to consider the problem of machine equivalence which defines two [[Synchronous circuit|synchronous design]] specifications functionally equivalent if, clock by clock, they produce ''exactly'' the same sequence of output signals for ''any'' valid sequence of input signals. 
*[[Microprocessor]] designers use equivalence checking to compare the functions specified for the [[instruction set]] architecture (ISA) with a [[register transfer level]] (RTL) implementation, ensuring that any program executed on both models will cause an identical update of the main memory content.  This is a more general problem.
*A system design flow requires comparison between a transaction level model (TLM), e.g., written in [[SystemC]] and its corresponding RTL specification. Such a check is becoming of increasing interest in a system-on-a-chip (SoC) design environment.