Editing Harvard architecture (section)

==Memory details==
In a Harvard architecture, there is no need to make the two memories share characteristics. In particular, the [[Word (computer architecture)|word]] width, timing, implementation technology, and [[memory address]] structure can differ. In some systems, instructions for pre-programmed tasks can be stored in [[read-only memory]] while data memory generally requires [[random-access memory|read-write memory]]. In some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses.

===Contrast with von Neumann architectures===
{{Main|Von Neumann architecture}}
In a system with a pure [[von Neumann architecture]], instructions and data are stored in the same memory, so instructions are fetched over the same data path used to fetch data. This means that a [[Central processing unit|CPU]] cannot simultaneously read an instruction and read or write data from or to the memory. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time,<ref name="ddj1" >"[http://www.drdobbs.com/386-vs-030-the-crowded-fast-lane/184407891?pgno=4 386 vs. 030: the Crowded Fast Lane]". ''Dr. Dobb's Journal'', January 1988.</ref> even without a [[Cache (computing)|cache]]. A Harvard architecture computer can thus be faster for a given circuit complexity because [[instruction fetch]]es and data access do not contend for a single memory pathway.

Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero. Instruction address zero might identify a twenty-four-bit value, while data address zero might indicate an eight-bit byte that is not part of that twenty-four-bit value.

===Contrast with modified Harvard architecture===
{{Main|Modified Harvard architecture}}
A [[modified Harvard architecture]] machine is very much like a Harvard architecture machine, but it relaxes the strict separation between instruction and data while still letting the CPU concurrently access two (or more) memory buses. The most common modification includes separate instruction and data [[CPU cache|caches]] backed by a common address space.  While the CPU executes from cache, it acts as a pure Harvard machine.  When accessing backing memory, it acts like a von Neumann machine (where code can be moved around like data, which is a powerful technique). This modification is widespread in modern processors, such as the [[ARM architecture]], [[Power ISA]] and [[x86]] processors.  It is sometimes loosely called a Harvard architecture, overlooking the  fact that it is actually "modified".

Another modification provides a pathway between the instruction memory (such as ROM or [[flash memory]]) and the CPU to allow words from the instruction memory to be treated as read-only data. This technique is used in some microcontrollers, including the [[Atmel AVR]]. This allows constant data, such as [[text string]]s or [[function table]]s, to be accessed without first having to be copied into data memory, preserving scarce (and power-hungry) data memory for read/write variables. Special [[machine language]] instructions are provided to read data from the instruction memory, or the instruction memory can be accessed using a peripheral interface.{{efn|The IAP lines of 8051-compatible microcontrollers from STC have dual ported Flash memory, with one of the two ports hooked to the instruction bus of the processor core, and the other port made available in the special function register region.}} (This is distinct from instructions which themselves embed constant data, although for individual constants the two mechanisms can substitute for each other.)