Editing IBM ROMP (section)

==History==
The [[Instruction set architecture|architectural]] work on the ROMP began in late spring of 1977, as a spin-off of [[IBM Research]]'s [[IBM 801|801]] RISC processor (hence the "Research" in the acronym). Most of the architectural changes were for cost reduction, such as adding 16-bit instructions for byte-efficiency. The original ROMP had a 24-bit architecture, but the instruction set was changed to 32 bits a few years into the development.<ref>{{cite book<!-- Citation bot-->|url=http://bitsavers.org/pdf/ibm/pc/rt/SA23-1057_IBM_RT_Personal_Computer_Technology_1986.pdf|first1=D.E.|last1=Waldecker|first2=P.Y.|last2=Woon|chapter=ROMP/MMU Technology Introduction|title=The IBM RT Personal Computer Technology, Form No. SA23-1057|editor-first=Frank|editor-last=Waters|page=44}}</ref>

The first chips were ready in early 1981, making ROMP the first industrial RISC. The processor was revealed at the [[International Solid-State Circuits Conference]] in 1984<ref name="Bambrick" /> ROMP first appeared in a commercial product as the processor for the [[IBM RT PC]] [[workstation]], which was introduced in 1986. To provide examples for RT PC production, volume production of the ROMP and its MMU began in 1985.<ref name="Bambrick" /> The delay between the completion of the ROMP design, and introduction of the RT PC was caused by overly ambitious software plans for the RT PC and its [[operating system]] (OS). This OS virtualized the hardware and could host multiple other operating systems. This technology, called [[Partial virtualization|virtualization]], while commonplace in [[Mainframe computer|mainframe]] systems, only began to gain traction in smaller systems in the 21st century. An improved CMOS version of the ROMP was first used in the [[IBM 6152 Academic System]] workstation, and later in some models of the RT PC.

[[IBM Research]] used the ROMP in its Research Parallel Processor Prototype (RP3), an early experimental scalable [[shared-memory multiprocessor]] that supported up to 512 processors first detailed in 1985; and the CMOS version in its ACE, an experimental NUMA multiprocessor that was operational in 1988.<ref>{{cite book |last1=Lerman |first1=G. |last2=Rudolph |first2=L. |title=Parallel Evolution of Parallel Processors |url=https://archive.org/details/parallelevolutio00lerm |url-access=limited |date=1993 |publisher=Springer Science & Business Media |isbn=9781461528562 |page=[https://archive.org/details/parallelevolutio00lerm/page/n152 146]}}</ref>