Editing IBM RS64 (section)

==History==
In 1990, the [[AS/400]] engineering team at [[IBM Rochester]] began work on a new architecture known as ''C-RISC'' (Commercial [[RISC]]) to replace the IMPI architecture of the AS/400.<ref name="inside-as400">{{cite book|title=Inside the AS/400, Second Edition|url=https://books.google.com/books?id=5DoPAAAACAAJ|isbn=978-1882419661|author=Frank G. Soltis|year=1997|publisher=Duke Press}}</ref><ref>{{cite mailing list|url=https://archive.midrange.com/mi400/200310/msg00008.html|title=Re: Re: MI emulator|author=Leif Svalgaard|date=2003-10-08|access-date=2021-02-26|mailing-list=MI400}}</ref> C-RISC was an evolution of the IMPI instruction set, extending the [[address space]] to 96 bits and adding some RISC instructions to speed up the more computationally intensive commercial applications that were being created for AS/400s. IBM president [[Jack Kuehler]] wanted the AS/400 team to use PowerPC, but they resisted, arguing that the existing 32/64-bit PowerPC instruction set would not enable a viable transition for OS/400 software and that the existing instruction set required extensions for the commercial applications on the AS/400. At Kuehler's insistence, a team at Rochester led by [[Frank Soltis]] investigated the feasibility of extending the PowerPC instruction set to support the needs of the AS/400 platform. These extensions became known as '''Amazon''' and were selected by IBM [[executive management]] for further development over continued development of C-RISC.<ref>{{cite magazine|url=http://iprodeveloper.com/systems-management/inside-powerpc|title=Inside the PowerPC AS|date=July 1, 1995|author1=Adam T. Stallman|author2=Frank G. Soltis|magazine=System iNEWS Magazine|archive-url=https://web.archive.org/web/20130831203807/http://iprodeveloper.com/systems-management/inside-powerpc|archive-date=August 31, 2013|url-status=dead}}</ref>

At the same time, the [[RS/6000]] developers were broadly expanding their product line to include systems which spanned from low-end [[workstations]], to [[mainframe]]-competitor large enterprise SMP systems, to clustered [[IBM RS/6000 SP]]  supercomputing systems. PowerPC processors developed in the [[AIM alliance]] suited the low-end RISC workstation and small server space well. But mainframe and large clustered supercomputing systems required more performance and [[reliability, availability and serviceability]] features than processors designed for [[Apple Power Mac]]s. Multiple processor designs were required to simultaneously meet the requirements of the cost-focused Apple Power Mac, high-performance and RAS RS/6000 systems, and the AS/400 transition to PowerPC.

Amazon was extended to support those features as well, so that processors could be designed for use in both high-end RS/6000 and AS/400 machines.

The project to develop the first such processor was "Bellatrix" (the name of [[Bellatrix|a star in the Orion constellation]], also called the "Amazon Star"). The Bellatrix project was extremely ambitious in its pervasive use of self-timed & pulse-based circuits and the EDA tools required to support this design strategy, and was eventually terminated.  To address technical workstation, [[supercomputer]], and engineering/scientific markets, IBM Austin (the home of the RS/6000s) then started developing a time-to-market single-chip version of the Power2 (P2SC) in parallel with the development of a sophisticated 64-bit PowerPC processor with the POWER2 extensions and twin sophisticated MAF [[floating-point unit]]s (the POWER3/630). To address RS/6000 commercial applications and AS/400 systems, IBM Rochester (the home of the AS/400s) started developing the first of the high-end 64-bit PowerPC processors with AS/400 extensions, and IBM Endicott started developing a low-end single-chip PowerPC processor with AS/400 extensions.