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Instruction set architecture
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==Overview== An instruction set architecture is distinguished from a [[microarchitecture]], which is the set of [[processor design]] techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the [[Intel]] [[P5 (microarchitecture)|Pentium]] and the [[AMD]] [[Athlon]] implement nearly identical versions of the [[x86 instruction set]], but they have radically different internal designs. The concept of an ''architecture'', distinct from the design of a specific machine, was developed by [[Fred Brooks]] at IBM during the design phase of [[System/360]]. {{quote|Prior to NPL [System/360], the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.<ref name=Pugh>{{cite book|last1=Pugh|first1=Emerson W.|last2=Johnson|first2=Lyle R.|last3=Palmer|first3=John H.|title=IBM's 360 and Early 370 Systems|url=https://archive.org/details/ibms360early370s0000pugh|url-access=registration|year=1991|publisher=MIT Press|isbn=0-262-16123-0}}</ref>{{rp|p.137}}}} Some [[virtual machine]]s that support [[bytecode]] as their ISA such as [[Smalltalk]], the [[Java virtual machine]], and [[Microsoft]]'s [[Common Language Runtime]], implement this by translating the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see: [[Just-in-time compilation]]). [[Transmeta]] implemented the x86 instruction set atop [[very long instruction word]] (VLIW) processors in this fashion.
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