Editing Integrated circuit packaging (section)

== Design considerations ==
[[File:TSSOP RQFP SO SSOP QFN.jpg|thumb|right|Various IC packages (left to right): TSSOP-32, TQFP-100, SO-20, SO-14, SSOP-28, SSOP-16, SO-8, QFN-28]]

=== Electrical ===
The current-carrying traces that run out of the die, through the package, and into the [[printed circuit board]] (PCB) have very different electrical properties compared to on-chip signals.  They require special design techniques and need much more electric power than signals confined to the chip itself. Therefore, it is important that the materials used as electrical contacts exhibit characteristics like low resistance, low capacitance and low inductance.<ref name=":02"/> Both the structure and materials must prioritize signal transmission properties, while minimizing any [[Parasitic element (electrical networks)|parasitic elements]] that could negatively affect the signal.

Controlling these characteristics is becoming increasingly important as the rest of technology begins to speed up. Packaging delays have the potential to make up almost half of a high-performance computer's delay, and this bottleneck on speed is expected to increase.<ref name=":02">{{Cite book|title=Digital Integrated Circuits|last=Rabaey|first=Jan|publisher=Prentice Hall, Inc.|year=2007|isbn=978-0130909961|url-access=registration|url=https://archive.org/details/agilesoftwaredev00robe|edition=2nd}}</ref>

=== Mechanical and thermal ===
The [[integrated circuit]] package must resist physical breakage, keep out moisture, and also provide effective heat dissipation from the chip. Moreover, for [[RF]] applications, the package is commonly required to shield [[electromagnetic interference]], that may either degrade the circuit performance or adversely affect neighboring circuits. Finally, the package must permit interconnecting the chip to a [[Printed circuit board|PCB]].<ref name=":02"/> The materials of the package are either plastic ([[thermosetting polymer|thermoset]] or [[thermoplastic]]), metal (commonly [[Kovar]]) or ceramic. A common [[plastic]] used for this is [[epoxy]]-[[cresol]]-[[novolak]] (ECN).<ref>{{cite book |chapter-url=https://www.researchgate.net/publication/285397294 |doi=10.1016/B978-0-8155-1576-0.50006-1 |via=[[ResearchGate]]|chapter=Plastic Encapsulant Materials |title=Encapsulation Technologies for Electronic Applications |year=2009 |last1=Ardebili |first1=Haleh |last2=Pecht |first2=Michael G. |pages=47–127 |isbn=9780815515760 |s2cid=138753417 }}</ref> All three material types offer usable mechanical strength, moisture and heat resistance. Nevertheless, for higher-end devices, metallic and ceramic packages are commonly preferred due to their higher strength (which also supports higher pin-count designs), heat dissipation, [[hermetic seal|hermetic performance]], or other reasons.  Generally, ceramic packages are more expensive than similar plastic packages.<ref name=":1">{{Cite book|title=Integrated Circuit Packaging, Assembly and Interconnections|last=Greig|first=William|publisher=Springer Science & Business Media|year=2007|isbn=9780387339139}}</ref>

Some packages have [[Fin (extended surface)|metallic fins]] to enhance heat transfer, but these take up space. Larger packages also allow for more interconnecting pins.<ref name=":02"/>

=== Economic ===
Cost is a factor in selection of integrated circuit packaging. Typically, an inexpensive plastic package can dissipate heat up to 2W, which is sufficient for many simple applications, though a similar ceramic package can dissipate up to 50W in the same scenario.<ref name=":02"/> As the chips inside the package get smaller and faster, they also tend to get hotter. As the subsequent need for more effective heat dissipation increases, the cost of packaging rises along with it. Generally, the smaller and more complex the package needs to be, the more expensive it is to manufacture.<ref name=":1" /> Wire bonding can be used instead of techniques such as flip-chip to reduce costs.<ref>{{cite web | url=https://sst.semiconductor-digest.com/2005/07/wire-bond-vs-flip-chip-packaging/ | title=Wire Bond Vs. Flip Chip Packaging &#124; Semiconductor Digest | date=10 December 2016 }}</ref>