Editing Intel 8085 (section)

==Description==
[[Image:Intel 8085 arch.svg|right|thumb|i8085 microarchitecture]]
[[File:Anschlussbelegung 8085.svg|right|thumb|i8085 pinout]]
The 8085 is a conventional [[Von Neumann architecture|von Neumann]] design based on the Intel 8080. Unlike the 8080 it does not multiplex state signals onto the data bus, but the 8-bit [[Bus (computing)|data bus]] is instead multiplexed with the lower eight bits of the 16-bit [[address bus]] to limit the number of pins to 40. State signals are provided by dedicated bus control signal pins and two dedicated bus state ID pins named S0 and S1.  Pin 40 is used for the power supply (+5&nbsp;V) and pin 20 for ground. Pin 39 is used as the Hold pin.

The Intel 8085 processor was designed using [[NMOS logic|nMOS]] circuitry, with later "H" versions implemented in Intel's enhanced nMOS process known as [[Depletion-load NMOS logic#Intel HMOS|HMOS II]] ("High-performance MOS"), which was originally developed for fast static RAM products.<ref name="auto1">Intel Corporation, "New Products: HMOS MCS-85 Chips Uses 20 to 30 Percent Less Power", Solutions, July/August 1981, Page 22</ref> Unlike the 8080, the 8085 requires only a single 5-volt power supply, similar to its competing processors. The 8085 contains approximately 6,500 [[transistor]]s.<ref>The history of the microcomputer-invention and evolution, S Mazor - Proceedings of the IEEE, 1995</ref>

The 8085 incorporates the functions of the 8224 (clock generator) and the 8228 (system controller) on chip, increasing the level of integration. A downside compared to similar contemporary designs (such as the Z80) is the fact that the buses require demultiplexing; however, address latches in the Intel 8155, 8355, and 8755 memory chips allow a direct interface, so an 8085 along with these chips is almost a complete system.

The 8085 has extensions to support new [[interrupt]]s, with three maskable vectored interrupts (RST 7.5, RST 6.5 and RST 5.5), one [[non-maskable interrupt]] (TRAP), and one externally serviced interrupt (INTR). Each of these five interrupts has a separate pin on the processor, a feature which permits simple systems to avoid the cost of a separate interrupt controller. The RST 7.5 interrupt is edge triggered (latched), while RST 5.5 and 6.5 are level-sensitive. All interrupts except TRAP are enabled by the EI instruction and disabled by the DI instruction.  In addition, the SIM (Set Interrupt Mask) and RIM (Read Interrupt Mask) instructions, the only instructions of the 8085 that are not from the 8080 design, allow each of the three maskable RST interrupts to be individually masked.  All three are masked after a normal CPU reset. SIM and RIM also allow the global interrupt mask state and the three independent RST interrupt mask states to be read, the pending-interrupt states of those same three interrupts to be read, the RST 7.5 trigger-latch flip-flop to be reset (cancelling the pending interrupt without servicing it), and serial data to be sent and received via the SOD and SID pins, respectively, all under program control and independently of each other.

SIM and RIM each execute in four clock cycles (T states), making it possible to sample SID and/or toggle SOD considerably faster than it is possible to toggle or sample a signal via any I/O or memory-mapped port, e.g. one of the port of an 8155.  (In this way, SID can be compared to the SO ["Set Overflow"] pin of the 6502 CPU contemporary to the 8085.)

Like the 8080, the 8085 can accommodate slower memories through externally generated [[wait state]]s (pin 35, READY), and has provisions for [[Direct Memory Access]] (DMA) using HOLD and HLDA signals (pins 39 and 38). An improvement over the 8080 is that the 8085 can itself drive a [[piezoelectric crystal]] directly connected to it, and a built-in clock generator generates the internal high-amplitude [[two-phase clock]] signals at half the crystal frequency (a 6.14&nbsp;MHz crystal would yield a 3.07&nbsp;MHz clock, for instance). The internal clock is available on an output pin, to drive peripheral devices or other CPUs in lock-step synchrony with the CPU from which the signal is output.  The 8085 can also be clocked by an external [[Electronic oscillator|oscillator]] (making it feasible to use the 8085 in synchronous multi-processor systems using a system-wide common clock for all CPUs, or to synchronize the CPU to an external time reference such as that from a video source or a high-precision time reference).

The 8085 is a [[binary compatible]] follow-up on the 8080. It supports the complete [[instruction set]] of the 8080, with exactly the same instruction behavior, including all effects on the CPU flags (except for the AND/ANI operation, which sets the AC flag differently).<ref>{{cite book|url=http://www.bitsavers.org/components/intel/MCS80/MCS80_85_Users_Manual_Jan83.pdf |archive-url=https://web.archive.org/web/20170829032438/http://www.bitsavers.org/components/intel/MCS80/MCS80_85_Users_Manual_Jan83.pdf |archive-date=2017-08-29 |url-status=live|title=The MCS-80/85 Family User's Manual|date=January 1983|publisher=[[Intel]]|at=pp. 1–8|quote=The 8085A CPU is 100% software compatible with the Intel 8080A CPU.}}</ref> This means that the vast majority of object code (any program image in ROM or RAM) that runs successfully on the 8080 can run directly on the 8085 without translation or modification. (Exceptions include timing-critical code and code that is sensitive to the aforementioned difference in the AC flag setting or differences in undocumented CPU behavior.) 8085 instruction timings differ slightly from the 8080—some 8-bit operations, including INR, DCR, and the heavily used MOV r,r instructions, are one clock cycle faster, but instructions that involve 16-bit operations, including stack PUSH (which decrements the 16-bit SP register) generally one cycle slower. Conditional jumps not taken are three clocks faster on the 8085. As mentioned already, only the SIM and RIM instructions were new to the 8085.<ref group="nb">Note that the Z80 assigns different instructions—two of the Z80's 6 relative jumps—to the opcodes that the 8085 uses for RIM and SIM, making 8085 programs that use these instructions generally unable to run on the Z80 without modification.  Since use of these instructions usually relates to 8085-specific hardware features, the necessary program modification would typically be nontrivial.</ref>

===Programming model===
{| class="infobox" style="font-size:88%;width:34em;"
|-
|+ Intel 8085 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit position)''
|-
|colspan="17" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| A
| style="text-align:center;background:#DDD" colspan="8"| [[Flag (computing)|Flags]]
| style="width:auto; background:white; color:black;"| '''P'''rogram '''S'''tatus '''W'''ord
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| B
| style="text-align:center;" colspan="8"| C
| style="background:white; color:black;"| '''B'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| D
| style="text-align:center;" colspan="8"| E
| style="background:white; color:black;"| '''D'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| H
| style="text-align:center;" colspan="8"| L
| style="background:white; color:black;"| '''H''' (indirect address)
|-
|colspan="17" | '''[[Index registers]]'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| SP
| style="background:white; color:black;"| '''S'''tack '''P'''ointer
|-
|colspan="17" | '''[[Program counter]]'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|-
|colspan="17" | '''[[Status register]]'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="8" | &nbsp;
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Half-carry flag|AC]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Carry flag|CY]]
| style="background:white; color:black" | Flags
|}
|}

The processor has seven 8-bit [[processor register|registers]] accessible to the programmer, named A, B, C, D, E, H, and L, where A is also known as the accumulator. The other six registers can be used as independent byte-registers or as three 16-bit register pairs, BC, DE, and HL (or B, D, H, as referred to in Intel documents), depending on the particular instruction.

Some instructions use HL as a (limited) 16-bit accumulator. As in the 8080, the contents of the memory address pointed to by HL can be accessed as pseudo register M. It also has a 16-bit [[program counter]] and a 16-bit [[Stack-based memory allocation|stack pointer]] to memory (replacing the 8008's internal [[stack (data structure)|stack]]). Instructions such as PUSH PSW, POP PSW affect the Program Status Word (accumulator and flags). The accumulator stores the results of arithmetic and logical operations, and the flags register bits (sign, zero, auxiliary carry, parity, and carry flags) are set or cleared according to the results of these operations. The sign flag is set if the result has a negative sign (i.e. it is set if bit 7 of the accumulator is set). The auxiliary or half carry flag is set if a carryover from bit 3 to bit 4 occurred. The parity flag is set to 1 if the parity (number of 1-bits) of the accumulator is even; if odd, it is cleared. The zero flag is set if the result of the operation was 0. Lastly, the carry flag is set if a carryover from bit 7 of the accumulator (the MSB) occurred.

===Commands/instructions===
As in many other 8-bit processors, all instructions are encoded in a single byte (including register-numbers, but excluding immediate data), for simplicity. Some of them are followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. A NOP "no operation" instruction exists, but does not modify any of the registers or flags. Like larger processors, it has CALL and RET instructions for multi-level procedure calls and returns (which can be conditionally executed, like jumps) and instructions to save and restore any 16-bit register-pair on the machine stack. There are also eight one-byte call instructions (RST) for subroutines located at the fixed addresses 00h, 08h, 10h,...,38h. These are intended to be supplied by external hardware in order to invoke a corresponding interrupt-service routine, but are also often employed as fast system calls. One sophisticated instruction is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.

====8-bit instructions====
All two-operand 8-bit arithmetic and logical (ALU) operations work on the 8-bit [[Accumulator (computing)|accumulator]] (the A register). For two-operand 8-bit operations, the other operand can be either an immediate value, another 8-bit register, or a memory cell addressed by the 16-bit register pair HL. The only 8-bit ALU operations that can have a destination other than the accumulator are the unary incrementation or decrementation instructions, which can operate on any 8-bit register or on memory addressed by HL, as for two-operand 8-bit operations. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory cell, using the MOV instruction. An immediate value can also be moved into any of the foregoing destinations, using the MVI instruction. Due to the regular encoding of the MOV instruction (using nearly a quarter of the entire opcode space) there are redundant codes to copy a register into itself (''MOV B,B'', for instance), which are of little use, except for delays.<ref group="nb">Even so, there is no need for seven different effectively identical delay instructions, and they are also identical in effect and form to the NOP instruction, except that NOP conveniently has the opcode 00 hex.</ref> However, what would have been a copy from the HL-addressed cell into itself (i.e., ''MOV M,M'') instead encodes the [[HLT (x86 instruction)|HLT]] instruction, halting execution until an external reset or unmasked interrupt occurs.<ref group="nb">(The TRAP interrupt, being an [[Non-maskable interrupt|NMI]], can always bring the 8085 out of the HALT state.)</ref> <!-- It would be better if HLT were only mentioned here as regards opcode assignment and was explained operationally in a separate section about machine-control instructions-->

====16-bit operations====
Although the 8085 is an 8-bit processor, it has some 16-bit operations. Any of the three 16-bit register pairs (BC, DE, HL) or SP can be loaded with an immediate 16-bit value (using LXI), incremented or decremented (using INX and DCX), or added to HL (using DAD). LHLD loads HL from directly addressed memory and SHLD stores HL likewise. The XCHG operation exchanges the values of HL and DE. XTHL exchanges last item pushed on stack with HL. Adding HL to itself performs a 16-bit arithmetic left shift with one instruction. The only 16-bit instruction that affects any flag is DAD (adding BC, DE, HL, or SP to HL), which updates the carry flag to facilitate 24-bit or larger additions and left shifts. Adding the stack pointer to HL is useful for indexing variables in (recursive) stack frames. A stack frame can be allocated using DAD SP and SPHL, and a branch to a computed pointer can be done with PCHL. These abilities make it feasible to compile languages such as [[PL/M]], [[Pascal (programming language)|Pascal]], or [[C (programming language)|C]] with 16-bit variables and produce 8085 machine code. Subtraction and bitwise logical operations on 16 bits is done in 8-bit steps. Operations that have to be implemented by program code (subroutine libraries) include comparisons of signed integers as well as multiplication and division.

====Undocumented instructions====
A number of undocumented instructions and flags were discovered by two software engineers, Wolfgang Dehnhardt and Villy M. Sorensen in the process of developing an 8085 assembler. These instructions use 16-bit operands and include indirect loading and storing of a word, a subtraction, a shift, a rotate, and offset operations.<ref>{{cite journal
 | first1 = Wolfgang
 | last1 = Dehnhardt
 | first2 = Villy
 | last2 = M. Sorensen
 | title = Unspecified 8085 op codes enhance programming
 | journal = Electronics
 | publisher = McGraw-Hill
 | date = January 1979
 | pages = 144–145
 | issn = 0013-5070
 | url = http://www.club100.org/memfiles/index.php?action=downloadfile&filename=UnDoc85.pdf&directory=Steve%20Adolph/undocumented_8085_opcodes
}}</ref>

By the time 8085 was designed but not yet announced, many designers found it to be inferior to the competing products already on the market. The next generation 16-bit 8086 CPU was already in development. Intel made a last minute decision to leave 10 out of 12 new 8085 instructions undocumented to speed up and simplify the design of the upcoming 8086 CPU.<ref>
{{cite journal
 | first1 = Stanley
 | last1 = Mazor
 | title = Intel's 8086
 | journal = IEEE Annals of the History of Computing
 | publisher = IEEE Computer Society
 | date = January–March 2010
 | volume = 32
 | pages = 75–79
 | doi = 10.1109/MAHC.2010.22
 | issn = 1058-6180
 | url = https://ieeexplore.ieee.org/document/5430762
| url-access = subscription
 }}
</ref>

===Input/output scheme===
The 8085 supports both [[Memory-mapped I/O|port-mapped and memory-mapped I/O]]. It supports up to 256 [[input/output]] (I/O) ports via dedicated Input/Output instructions, with port addresses as operands. Port-mapped IO can be an advantage on processors with limited address space. During a port-mapped I/O bus cycle, the 8-bit I/O address is output by the CPU on both the lower and upper halves of the 16-bit address bus.

Devices designed for memory mapped I/O can also be accessed by using the LDA (load accumulator from a 16-bit address) and STA (store accumulator at a 16-bit address specified) instructions, or any other instructions that have memory operands. A memory-mapped IO transfer cycle appears on the bus as a normal memory access cycle.

===Development system===
{{Main|Intel system development kit}}
Intel produced a series of development systems for the 8080 and 8085, known as the MDS-80 Microprocessor System. The original development system had an 8080 processor. Later 8085 and 8086 support was added including ICE ([[in-circuit emulator]]s). It is a large and heavy desktop box, about a 20" cube (in the Intel corporate blue color) which includes a CPU, monitor, and a single 8-inch floppy disk drive. Later an external box was made available with two more floppy drives. It runs the [[ISIS (operating system)|ISIS]] operating system and can also operate an [[emulator]] pod and an external [[EPROM]] programmer. This unit uses the Multibus card cage which was intended just for the development system. A surprising number of spare card cages and processors were being sold, leading to the development of the Multibus as a separate product.

The later iPDS is a portable unit, about 8"{{times}}16"{{times}}20", with a handle. It has a small green screen, a keyboard built into the top, a 5¼ inch floppy disk drive, and runs the ISIS-II operating system. It can also accept a second 8085 processor, allowing a limited form of multi-processor operation where both processors run simultaneously and independently. The screen and keyboard can be switched between them, allowing programs to be assembled on one processor (large programs took a while) while files are edited in the other. It has a [[bubble memory]] option and various programming modules, including EPROM, and [[Intel 8048]] and [[Intel 8051|8051]] programming modules which are plugged into the side, replacing stand-alone device programmers. In addition to an 8080/8085 assembler, Intel produced a number of compilers including those for [[PL/M|PL/M-80]] and [[Pascal programming language|Pascal]], and a set of tools for linking and statically locating programs to enable them to be burned into [[EPROM]]s and used in [[embedded system]]s.

A lower cost "MCS-85 System Design Kit" (SDK-85) board contains an 8085 CPU, an 8355 ROM containing a debugging monitor program, an 8155 RAM and 22 I/O ports, an 8279 hex keypad and 8-digit 7-segment LED, and a TTY (Teletype) {{val|20|ul=mA}} current loop serial interface. Pads are available for one more 2K×8 8755 EPROM, and another {{val|256|ul=byte}} RAM 8155 I/O Timer/Counter can be optionally added. All data, control, and address signals are available on dual pin headers, and a large prototyping area is provided.

===List of Intel 8085 Models===
{| class="wikitable"
|-
! Model Number !! Technology Process || Process Node || Clock Speed || Temperature Range !! Current Rating || Power Tolerance || Package || Date of Release !! Price USD<ref group=list>In quantities of 100 and up</ref>
|-
| 8085A<ref name="auto1"/> || [[Depletion-load NMOS logic#Depletion-mode transistors|NMOS]] || [[3 μm process|3 micron]] || 3&nbsp;MHz || || 170 mA || ± 5% || || || $6.25
|-
| P8085AH<ref name="auto1"/> || [[Depletion-load NMOS logic#Intel HMOS|HMOS II]] || 2 micron || 3&nbsp;MHz || || 135 mA || ± 10% || Plastic || July/August 1981 || $4.40
|-
| 8085-2<ref name="January/February 1980">Intel Corporation, "New EPROM completes 5MHz capability for MCS-85™ family", Intel Preview, January/February 1980, p. 24.</ref> || || || 5&nbsp;MHz || || || || || ||
|-
| 8085A-2<ref name="auto1"/> || NMOS || 3 micron || 5&nbsp;MHz || || 170 mA || ± 5% || || || $8.75
|-
| P8085AH-2<ref name="auto1"/> || HMOS II || 2 micron || 5&nbsp;MHz || || 135 mA || ± 10% || Plastic || July/August 1981 || $5.80
|-
| P8085AH-1<ref name="auto1"/> || HMOS II || 2 micron || 6&nbsp;MHz || || || || Plastic || July/August 1981 || $12.45
|-
| ID8085<ref name="March/April 1979-p11">Intel Corporation, "Microcomputer Component: New industrial grade product line answers the demand for high-reliability components to operate in industrial applications.", Intel Preview, March/April 1979, p. 11.</ref> || || || 3&nbsp;MHz || Industrial || || || || March/April 1979 || $38.75
|-
| M8085A<ref name="auto">Intel Corporation, "Military Products: Intel marches on!", Intel Preview, March/April 1979, p. 19.</ref> || || || 3&nbsp;MHz || Military || || || || March/April 1979 || $110.00
|-
|}

{{reflist|group=list}}