Editing Intel MCS-48 (section)

== Variants ==
The '''8049''' has 2&nbsp;KB of masked [[read-only memory|ROM]] (the 8748 and 8749 had [[EPROM]]) that can be replaced with a 4&nbsp;KB external ROM, as well as 128&nbsp;[[byte]]s of [[random-access memory|RAM]] and 27&nbsp;[[input/output|I/O]] ports.{{sfn|Intel Corporation|1978}} The microcontroller's [[Electronic oscillator|oscillator]] block divides the clock input frequency by three and then further divides the result into five machine states. Using the 11&nbsp;[[megahertz|MHz]] maximum crystal frequency will produce 0.73&nbsp;[[Instructions per second#Millions of instructions per second (MIPS)|MIPS]] of single-cycle [[instruction set architecture|instruction]]s. Some 70% of instructions are single byte and single cycle ones, but 30% need two cycles or two bytes, so its typical performance would be closer to 0.5&nbsp;MIPS.

{| class="wikitable"
|+Microcontroller{{fact|date=November 2022}}
! Device !! Internal           !! Memory      !! Remarks
|-
| 8020   || 1K × 8 ROM         || 64 × 8 RAM  || subset of 8048, 20 pins, only 13 I/O lines
|-
| 8021   || 1K × 8 ROM         || 64 × 8 RAM  || subset of 8048, 28 pins, 21 I/O lines
|-
| 8022   || 2K × 8 ROM         || 64 × 8 RAM  || subset of 8048, A/D-converter
|-
| 8035   || none               || 64 × 8 RAM  ||
|-
| 8038   || none               || 64 × 8 RAM  ||
|-
| 8039   || none               || 128 × 8 RAM ||
|-
| 8040   || none               || 256 × 8 RAM ||
|-
| 8048   || 1K × 8 ROM         || 64 × 8 RAM  || 27×&nbsp;I/O ports
|-
| 8049   || 2K × 8 ROM         || 128 × 8 RAM || 27×&nbsp;I/O ports
|-
| 8050   || 4K x 8 ROM         || 256 × 8 RAM ||
|-
| 8648   || 1K × 8 OTP EPROM   || 64 × 8 RAM  || Factory OTP EPROM
|-
| 8748   || 1K × 8 EPROM<ref name="CompArchOrg">{{cite book |title=Computer Architecture and Organization  |last=Hayes |first=John P. |isbn=0-07-027363-4 |date=1978 |publisher=McGraw-Hill International Book Company |pages=57-59}}</ref>       || 64 × 8 RAM<ref name="CompArchOrg"/>  || 4K program memory expandable,<ref name="CompArchOrg"/> 2×&nbsp;8-bit timers, 27×&nbsp;I/O ports
|-
| 8749   || 2K × 8 EPROM       || 128 × 8 RAM || 2×&nbsp;8-bit timers, 27×&nbsp;I/O ports
|-
| 87P50  || ext. ROM socket    || 256 × 8 RAM || Has [[piggyback microcontroller|piggy-back socket]] for 2758/2716/2732 EPROM
|}

[[File:Intel P8242.jpg|thumb|Intel P8242 - keyboard controller with Phoenix firmware for AT-compatible computers]]
[[File:NS87P50D-6.jpg|thumb|[[National Semiconductor]] NS87P50D-6 – [[Second source]] for the 87P50 [[piggyback microcontroller]]]]
{| class="wikitable"
|+Universal Peripheral Interface
! Device !! Internal           !! Memory      !! Remarks
|-
| 8041    || 1K × 8 ROM        || 64 × 8 RAM  || Universal Peripheral Interface (UPI)
|-
| 8041AH  || 1K × 8 ROM        || 128 × 8 RAM || UPI
|-
| 8741A   || 1K × 8 EPROM      || 64 × 8 RAM  || UPI, EPROM version of 8041
|-
| 8741AH  || 1K × 8 OTP EPROM  || 128 × 8 RAM || UPI, OTP EPROM version of 8041AH
|-
| 8042AH  || 2K × 8 ROM        || 256 × 8 RAM || UPI
|-
| 8242    || 2K × 8 ROM        || 256 × 8 RAM || UPI, preprogrammed with keyboard controller firmware<ref>{{cite web |url=https://datasheet.datasheetarchive.com/originals/scans/Scans-007/Scans-00146940.pdf |title=UPI-41AH/42AH Universal Peripheral Interface 8-bit Slave Microcontroller |publisher=Intel |date=November 1994 |access-date=2022-07-19 |page=2}}</ref>
|-
| 8742    || 2K × 8 EPROM      || 128 × 8 RAM || UPI, EPROM version
|-
| 8742AH  || 2K × 8 OTP EPROM  || 256 × 8 RAM || UPI, OTP EPROM version of 8042AH
|}