Editing Intel iAPX 432 (section)

==Description==
The iAPX 432 was referred to as a "micromainframe", designed to be programmed entirely in high-level languages.<ref name=Intel81>{{Cite book|last=Intel Corporation|title=Introduction to the iAPX 432 Architecture|year=1981|pages=iii|url=http://bitsavers.org/components/intel/iAPX_432/171821-001_Introduction_to_the_iAPX_432_Architecture_Aug81.pdf}}</ref><ref name="i8800">{{Cite journal | doi = 10.1109/MAHC.2010.22 | title = Intel's 8086 | author = Stanley Mazor | journal = IEEE Annals of the History of Computing | volume = 32 | number = 1 | date = January–March 2010 | pages = 75–79| s2cid = 16451604 }}</ref> The [[instruction set architecture]] was also entirely new and a significant departure from Intel's previous [[8008]] and [[8080]] processors as the iAPX 432 programming model is a [[stack machine]] with no visible [[general-purpose register]]s. It supports [[object-oriented programming]],<ref name="i8800" /> [[Garbage collection (computer science)|garbage collection]] and [[computer multitasking|multitasking]] as well as more conventional [[memory management]] directly in hardware and [[microcode]]. Direct support for various [[data structure]]s is also intended to allow modern [[operating system]]s to be implemented using far less program [[machine code|code]] than for ordinary processors. Intel [[iMAX 432]] is a discontinued [[operating system]] for the 432,<ref>{{Cite journal | doi = 10.1145/800216.806601| last1 = Kahn | first1 = Kevin C.| last2 = Corwin | first2 = William M.| last3 = Dennis | first3 = T. Don| last4 = d'Hooge | first4 = Herman| last5 = Hubka | first5 = David E.| last6 = Hutchins | first6 = Linda A.| last7 = Montague | first7 = John T.| last8 = Pollack | first8 = Fred J.| url = https://cs.uwaterloo.ca/~Brecht/courses/702/Possible-Readings/oses/imax-multiprocessor-os-sosp-1981.pdf| title = iMAX: A multiprocessor operating system for an object-based computer| journal = ACM SIGOPS Operating Systems Review| volume = 15| issue = 5| date = December 1981| pages = 127–136| s2cid = 9245960 }}</ref> written entirely in [[Ada (programming language)|Ada]], and Ada was also the intended primary language for application programming. In some aspects, it may be seen as a [[high-level language computer architecture]].

These properties and features resulted in a hardware and microcode design that was more complex than most processors of the era, especially microprocessors. However, internal and external buses are (mostly) not wider than [[16-bit]], and, as in some other 32-bit microprocessors of the era such as the [[Motorola 68000|68000]], 32-bit arithmetic instructions are implemented by a 16-bit ALU, via [[random logic]] and [[microcode]] or other kinds of [[sequential logic]]. The iAPX 432 enlarged address space over the 8080 was also limited by the fact that ''[[linear addressing]]'' of data could still only use 16-bit offsets, somewhat akin to Intel's first [[Intel 8086|8086]]-based designs, including the contemporary [[Intel 80286|80286]] (the new 32-bit segment offsets of the [[Intel 80386|80386]] architecture was described publicly in detail in 1984).<ref group="NB">although the 80386 chip was not mass produced until mid 1986</ref>

Using the semiconductor technology of its day, Intel's engineers weren't able to translate the design into a very efficient first implementation. Along with the lack of optimization in a premature [[Ada (programming language)|Ada]] compiler, this contributed to rather slow but expensive computer systems, performing typical benchmarks at roughly 1/4 the speed of the new [[80286]] chip at the same clock frequency (in early 1982).<ref name="performance-effects"/> This initial performance gap to the rather low-profile and low-priced [[8086]] line was probably the main reason why Intel's plan to replace the latter (later known as [[x86]]) with the iAPX 432 failed. Although engineers saw ways to improve a next generation design, the iAPX 432 ''[[Capability-based security|capability architecture]]'' had now started to be regarded more as an implementation overhead rather than as the simplifying support it was intended to be.<ref name="performance-effects">{{Cite journal | doi = 10.1145/45059.214411| last1 = Colwell | first1 = Robert| last2 = Gehringer | first2 = Edward| year = 1988| title = Performance Effects of Architectural Complexity in the Intel 432| journal =  ACM Transactions on Computer Systems| volume = 6| issue = 3| pages = 296–339| s2cid = 8314206 | url = http://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings/I432.pdf}}</ref>

Originally designed for clock frequencies of up to 10&nbsp;MHz, actual devices sold were specified for maximum clock speeds of 4&nbsp;MHz, 5&nbsp;MHz, 7&nbsp;MHz and 8&nbsp;MHz with a peak performance of 2&nbsp;million instructions per second at 8&nbsp;MHz.<ref>[http://www.brouhaha.com/~eric/retrocomputing/intel/iapx432/ Intel iAPX-432 Micromainframe]</ref><ref>{{cite web|url=http://electronicdesign.com/boards/ten-notable-flops-learning-mistakes|title=Ten Notable Flops: Learning From Mistakes|publisher=Electronic Design|first1=Lisa|last1=Maliniak|date=October 21, 2002}}</ref>