Editing Itanium (section)

== History ==
=== Development: 1989–2001 ===
==== Inception: 1989–1994 ====
In 1989, HP started to research an architecture that would exceed the expected limits of the [[reduced instruction set computer]] (RISC) architectures caused by the great increase in complexity needed for executing multiple [[instructions per cycle]] due to the need for dynamic [[Data dependency|dependency]] checking and precise [[exception handling]].{{Efn|The size of the needed dependency-checking circuitry increases [[Quadratic growth|quadratically]] with the issue width.<ref name="simplicity"/><ref name="Understanding_EPIC"/>}} HP hired [[Bob Rau]] of [[Cydrome]] and [[Josh Fisher]] of [[Multiflow]], the pioneers of [[very long instruction word]] (VLIW) computing. One VLIW instruction word can contain several independent [[instruction (computer science)|instructions]], which can be executed in parallel without having to evaluate them for independence. A [[compiler]] must attempt to find [[Instruction-level parallelism|valid combinations of instructions that can be executed at the same time]], effectively performing the instruction scheduling that conventional [[superscalar processor]]s must do in hardware at runtime.

HP researchers modified the classic VLIW into a new type of architecture, later named [[Explicitly Parallel Instruction Computing]] (EPIC), which differs by: having template bits which show which instructions are independent inside and between the bundles of three instructions, which enables the explicitly parallel execution of multiple bundles and increasing the processors' [[Wide-issue|issue width]] without the need to recompile; by [[Predication (computer architecture)|predication]] of instructions to reduce the need for [[Branch (computer science)|branches]]; and by full interlocking to eliminate the [[delay slot]]s. In EPIC the assignment of [[execution unit]]s to instructions and the timing of their issuing can be decided by hardware, unlike in the classic VLIW. HP intended to use these features in PA-WideWord, the planned successor to their [[PA-RISC]] ISA. EPIC was intended to provide the best balance between the efficient use of silicon area and electricity, and general-purpose flexibility.<ref name="Understanding_EPIC">{{cite web |last1=Smotherman |first1=Mark |title=Understanding EPIC Architectures and Implementations |url=https://people.computing.clemson.edu/~mark/464/acmse_epic.pdf |publisher=[[Clemson University]] |access-date=5 June 2022}}</ref><ref name="HP_Labs">{{cite web
 | url=https://www.hpl.hp.com/news/2001/apr-jun/itanium.html
 | title=Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture
 | access-date=March 23, 2007
 | date=June 2001
 | work=[[HP Labs]]
 }}</ref> In 1993 HP held an internal competition to design the best (simulated) microarchitectures of a RISC and an EPIC type, led by Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] respectively. The EPIC team won, with over double the simulated performance of the RISC competitor.<ref name="nyt_merced">{{cite web |last1=Markoff |first1=John |title=Inside Intel, The Future is Riding on the Merced Chip |url=https://archive.org/details/TheJerusalemPost1998IsraelEnglish/Apr%2006%201998%2C%20The%20Jerusalem%20Post%2C%20%2319898%2C%20Israel%20%28en%29/page/n12/mode/1up |publisher=[[The New York Times]], republised by [[The Jerusalem Post]] |date=5 April 1998}}</ref>

At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the [[Intel i860|i860]], which it marketed for workstations, servers, and [[Intel iPSC#iPSC/860|iPSC]] and [[Intel Paragon|Paragon]] supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<ref>{{cite web |last1=DeMone |first1=Paul |title=Intel's History Lesson |url=https://www.realworldtech.com/intel-history-lesson/ |website=Real World Tech |date=25 January 2000}}</ref>

In November 1993 HP approached Intel, seeking collaboration on an innovative future architecture.<ref name="countdown">{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}}</ref>{{refn|{{cite web |last1=Alpert |first1=Donald |title=Intel Itanium Processor (Merced) |url=https://camelback-comparch.com/about/technical-highlights/#merced |date=July 2003}} Alpert was the chief architect of the original P7 and the top engineering manager of Merced<ref>{{cite web |last1=Smotherman |first1=Mark |title=Who are the Computer Architects? |url=https://people.computing.clemson.edu/~mark/architects.html |publisher=[[Clemson University]] }} See the sections "Independence architecture" and "Wintel".</ref>}} At the time Intel was looking to extend x86 to 64 bits in a processor codenamed P7, which they found challenging.<ref>{{cite web |last1=DeMone |first1=Paul |title=What's Up With Willamette? (Part 1) |url=https://www.realworldtech.com/willamette-basics/ |website=Real World Tech |date=3 March 2000}}</ref> Later Intel claimed that four different design teams had explored 64-bit extensions, but each of them concluded that it was not economically feasible.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel takes slow road to 64-bit PC chips |url=https://www.cnet.com/tech/tech-industry/intel-takes-slow-road-to-64-bit-pc-chips/ |website=[[CNET]] |date=21 February 2003}}</ref> At the meeting with HP, Intel's engineers were impressed when Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] presented the PA-WideWord architecture they had designed to replace [[PA-RISC]]. "When we saw WideWord, we saw a lot of things we had only been looking at doing, already in their full glory", said Intel's [[John Crawford (engineer)|John Crawford]], who in 1994 became the chief architect of Merced, and who had earlier argued against extending the x86 with P7. HP's Gupta recalled: "I looked Albert Yu [Intel's general manager for microprocessors] in the eyes and showed him we could run circles around [[PowerPC]], that we could kill PowerPC, that we could kill the x86."<ref name="gambles"/> Soon Intel and HP started conducting in-depth technical discussions at an HP office, where each side had six{{Refn|<ref name="countdown"/><ref name="birth">{{cite web |last1=Britt |first1=Russ |title=The birth of a new processor |url=https://www.edn.com/the-birth-of-a-new-processor/ |website=[[EDN (magazine)|EDN]] |date=1 January 2000}}</ref> (The {{Define|ACM|architecture, compilers, microarchitecture}} committee with 5 people from each side<ref>{{cite web |last1=Smotherman |first1=Mark |title=Historical background for EPIC instruction set architectures |url=https://people.computing.clemson.edu/~mark/epic.html |publisher=[[Clemson University]] |access-date=3 June 2022}}</ref> was probably a different entity.)}} engineers who exchanged and discussed both companies' confidential architectural research. They then decided to use not only PA-WideWord, but also the more experimental [[HP Labs]] PlayDoh as the source of their joint future architecture.<ref name="simplicity">{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/ |website=Real World Tech |date=27 October 1999}}</ref><ref>{{cite web |last1=Kathail |first1=Vinod |last2=Schlansker |first2=Michael S. |last3=Rau |first3=B. Ramakrishna |title=HPL-PD Architecture Specification: Version 1.1 |url=https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |publisher=[[HP Labs|HP Laboratories]] |access-date=2023-07-05 |archive-date=2024-02-04 |archive-url=https://web.archive.org/web/20240204063521/https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |url-status=dead }}</ref> Convinced of the superiority of the new project, in 1994 Intel canceled their existing plans for P7.

In June 1994 Intel and HP announced their joint effort to make a new ISA that would adopt ideas of Wide Word and VLIW. Yu declared: "If I were competitors, I'd be really worried. If you think you have a future, you don't."<ref name="gambles">{{cite web |last1=Hamilton |first1=David |title=Intel gambles with Itanium |url=https://www.zdnet.com/article/intel-gambles-with-itanium/ |website=[[ZDNet]] |date=28 May 2001}}</ref> On P7's future, Intel said the alliance would impact it, but "it is not clear" whether it would "fully encompass the new architecture".<ref>{{cite web |last1=Hecht |first1=Jeff |title=Technology: Intel opts for simpler, speedier chips |url=https://www.newscientist.com/article/mg14219303-300-technology-intel-opts-for-simpler-speedier-chips/ |website=[[New Scientist]] |date=18 June 1994}}</ref><ref>{{cite web |last1=Bozman |first1=Jean S. |title=Chip alliance shakes ground |url=https://books.google.com/books?id=QZtKFFB8weQC&pg=PA12 |website=[[Computerworld]] |date=13 June 1994}} David House had approved the project, but later severely criticized it.</ref>
Later the same month, Intel said that some of the first features of the new architecture would start appearing on Intel chips as early as the P7, but the full version would appear sometime later.<ref>{{cite web |last1=Babcock |first1=Charles |title=Silicon marriage: HP/Intel venture |url=https://books.google.com/books?id=QtpyKsPTNwkC&pg=PA6 |website=[[Computerworld]] |date=25 July 1994}}</ref>
In August 1994 [[EE Times]] reported that Intel told investors that P7 was being re-evaluated and possibly canceled in favor of the HP processor. Intel immediately issued a clarification, saying that P7 is still being defined, and that HP may contribute to its architecture. Later it was confirmed that the P7 codename had indeed passed to the HP-Intel processor. By early 1996 Intel revealed its new codename, ''Merced''.<ref>{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}} Has a typo (P'''5''') in the graphic.</ref><ref>{{cite web |last1=Crothers |first1=Brooke |title=Intel aims to bring multimedia to the masses |url=https://books.google.com/books?id=zD4EAAAAMBAJ&pg=PA8 |website=[[InfoWorld]] |date=29 January 1996}}</ref>

HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake the very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.<ref name="HP_Labs"/>

==== Design and delays: 1994–2001 ====
Merced was designed by a team of 500, which Intel later admitted was too inexperienced, with many recent college graduates. Crawford (Intel) was the chief architect, while Huck (HP) held the second position. Early in the development HP and Intel had a disagreement where Intel wanted more dedicated hardware for more floating-point instructions. HP prevailed upon the discovery of [[Pentium FDIV bug|a floating-point hardware bug]] in Intel's [[Pentium (original)|Pentium]]. When Merced was [[Floorplan (microelectronics)|floorplanned]] for the first time in mid-1996, it turned out to be far too large, "this was a lot worse than anything I'd seen before", said Crawford. The designers had to reduce the complexity (and thus performance) of subsystems, including the x86 unit and cutting the L2 cache to 96 KB.{{Efn|For comparison the 180nm Pentium III Xeon MP had a 2 MB on-die L2 cache.}} Eventually it was agreed that the size target could only be reached by using the [[180 nm]] process instead of the intended [[250 nm process|250 nm]]. Later problems emerged with attempts to speed up the critical paths without disturbing the other circuits' speed. Merced was [[Tape-out|taped out]] on 4 July 1999, and in August Intel produced the first complete test chip.<ref name="gambles"/>

The expectations for Merced waned over time as delays and performance deficiencies emerged, shifting the focus and onus for success onto the HP-led second Itanium design, codenamed ''McKinley''. In July 1997 the switch to the [[180 nm process]] delayed Merced into the second half of 1999.<ref>{{cite web |title=Merced "Will Be Out Late 1999," Says Hewlett-Packard |url=https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1 |agency=Computer Business Review |website=Tech Monitor |date=18 July 1997 |url-status=live |archive-url=https://archive.today/20240213040233/https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1 |archive-date= 13 February 2024 }}</ref> Shortly before the reveal of [[Explicitly parallel instruction computing|EPIC]] at the Microprocessor Forum in October 1997, an analyst of the [[Microprocessor Report]] said that Itanium would "not show the competitive performance until 2001. It will take the second version of the chip for the performance to get shown".<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel late to 64-bit computing |url=https://www.cnet.com/news/intel-late-to-64-bit-computing/ |website=[[CNET]] |date=6 October 1997 |url-status=live |archive-url=https://web.archive.org/web/20220627172827/https://www.cnet.com/tech/tech-industry/intel-late-to-64-bit-computing/ |archive-date= Jun 27, 2022 }}</ref> At the Forum, Intel's [[Fred Pollack]] originated the "wait for McKinley" mantra when he said that it would double the Merced's performance and would "knock your socks off",<ref name="cnet_unveil_epic">{{cite web |last1=Kanellos |first1=Michael |title=Intel, HP unveil EPIC technology |url=https://www.cnet.com/news/intel-hp-unveil-epic-technology/ |website=[[CNET]] |date=14 October 1997 |url-status=live |archive-url=https://web.archive.org/web/20220818183735/https://www.cnet.com/tech/tech-industry/intel-hp-unveil-epic-technology/ |archive-date= Aug 18, 2022 }}</ref><ref>{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/3/ |website=Real World Tech |page=3 |date=27 October 1999 |url-status=live |archive-url=https://web.archive.org/web/20231031163355/https://www.realworldtech.com/hp-intel-itanium/3/ |archive-date= Oct 31, 2023 }}</ref> while using the same 180 nm process as Merced.<ref>{{cite news |last1=Gwennap |first1=Linley |title=Intel, HP Make EPIC Disclosure |url=https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf |work=[[Microprocessor Report]] |volume=11 |issue=14 |date=27 October 1997 |url-status=live |archive-url= https://web.archive.org/web/20231031163335/https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf |archive-date= Oct 31, 2023 }}</ref> Pollack also said that Merced's x86 performance would be lower than the fastest x86 processors, and that x86 would "continue to grow at its historical rates".<ref name="cnet_unveil_epic"/> Intel said that IA-64 won't have much presence in the consumer market for 5 to 10 years.<ref>{{cite news |last1=Corcoran |first1=Elizabeth |title=Chipmakers unveil works in progress |url=https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/ |url-access=subscription |newspaper=[[The Washington Post]] |date=15 October 1997 |url-status=live |archive-url= https://archive.today/20240213044222/https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/|archive-date= 13 February 2024 }}</ref>

Later it was reported that HP's motivation when starting to design McKinley in 1996 was to have more control over the project so as to avoid the issues affecting Merced's performance and schedule.<ref name="zdnet_wait">{{cite web |last1=Robertson |first1=Chiyo |title=Merced: Worth the wait? What of McKinley? |url=https://www.zdnet.com/article/merced-worth-the-wait-what-of-mckinley/ |website=[[ZDNet]] |date=17 March 1999}}</ref><ref>{{cite web |last1=Matsumoto |first1=Craig |title=Intel outlines road to McKinley processor |url=https://www.eetimes.com/intel-outlines-road-to-mckinley-processor/ |website=[[EE Times]] |date=8 October 1998}}</ref> The design team finalized McKinley's project goals in 1997.<ref name="HP_McKinley_wp">{{cite CiteSeerX |title=Inside the Intel Itanium 2 Processor: a Hewlett Packard Technical White Paper |date=17 July 2002 | citeseerx=10.1.1.96.8209 }}</ref> In late May 1998 Merced was delayed to mid-2000, and by August 1998 analysts were questioning its commercial viability, given that McKinley would arrive shortly after with double the performance, as delays were causing Merced to turn into simply a development vehicle for the Itanium ecosystem. The "wait for McKinley" narrative was becoming prevalent.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Is Merced doomed? |url=https://www.cnet.com/tech/tech-industry/is-merced-doomed/ |website=[[CNET]] |date=6 August 1998}}</ref> The same day it was reported that due to the delays, HP would extend its line of PA-RISC [[PA-8000]] series processors from PA-8500 to as far as PA-8900.<ref>{{cite news |title=INTEL'S MERCED COULD BE ECLIPSED BY MCKINLEY FOLLOW-ON |url=https://techmonitor.ai/technology/intels_merced_could_be_eclipsed_by_mckinley_follow_on |newspaper=Tech Monitor |date=6 August 1998}}</ref> In October 1998 HP announced its plans for four more generations of PA-RISC processors, with PA-8900 set to reach 1.2 GHz in 2003.<ref>{{cite web |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=HP has two-pronged chip plan |url=http://cnet.com/news/0-1004-200-334214.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20001203183700/http://cnet.com/news/0-1004-200-334214.html |archive-date=2000-12-03 |date=13 October 1998}}</ref>

By March 1999 some analysts expected Merced to ship in volume only in 2001, but the volume was widely expected to be low as most customers would wait for McKinley.<ref name="zdnet_wait"/> In May 1999, two months before Merced's [[tape-out]], an analyst said that failure to tape-out before July would result in another delay.<ref>{{cite web |last1=Gary |first1=Gregory |title=IA 64 Update: Part 1 of 2 |url=https://www.edn.com/ia-64-update-part-1-of-2/ |website=[[EDN (magazine)|EDN]] |date=3 May 1999}}</ref> In July 1999, upon reports that the first silicon would be made in late August, analysts predicted a delay to late 2000, and came into agreement that Merced would be used chiefly for debugging and testing the IA-64 software. Linley Gwennap of [[Microprocessor Report|MPR]] said of Merced that "at this point, everyone is expecting it's going to be late and slow, and the real advance is going to come from McKinley. What this does is puts a lot more pressure on McKinley and for that team to deliver".<ref name="may_slip">{{cite web |last1=Shankland |first1=Stephen |title=Intel's Merced chip may slip further |url=http://news.cnet.com/news/0-1003-200-344601.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20000605083119/http://news.cnet.com/news/0-1003-200-344601.html |archive-date=2000-06-05 |date=8 July 1999}}</ref> By then, Intel had revealed that Merced would be initially priced at $5000.<ref>{{cite web |last1=Hamblen |first1=Matt |title=Intel: No Forced March to Merced |url=https://books.google.com/books?id=51iIcvzoX-AC&pg=PA61 |website=[[Computerworld]] |date=12 July 1999}}</ref> In August 1999 HP advised some of their customers to skip Merced and wait for McKinley.<ref>{{cite web |last1=Shankland |first1=Stephen |title=HP upgrade path bypasses Merced chip |url=http://news.cnet.com/news/0-1003-200-346220.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20000819022147/http://news.cnet.com/news/0-1003-200-346220.html |archive-date=2000-08-19 |date=19 August 1999}}</ref> By July 2000 HP told the press that the first Itanium systems would be for niche uses, and that "You're not going to put this stuff near your data center for several years."; HP expected its Itanium systems to outsell the PA-RISC systems only in 2005.<ref>{{cite web |last1=Shankland |first1=Stephen |title=HP moves slowly into world of Intel 64-bit processors |url=http://www.news.cnet.com/news/0-1003-200-2241414.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010210011931/http://www.news.cnet.com/news/0-1003-200-2241414.html |archive-date=2001-02-10 |date=11 July 2000}}</ref> The same July Intel told of another delay, due to a [[Stepping level|stepping]] change to fix bugs. Now only "pilot systems" would ship that year, while the general availability was pushed to the "first half of 2001". Server makers had largely forgone spending on the R&D for the Merced-based systems, instead using motherboards or whole servers of Intel's design. To foster a wide ecosystem, by mid-2000 Intel had provided 15,000 Itaniums in 5,000 systems to software developers and hardware designers.<ref>{{cite web |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel pushes back schedule for Itanium chip |url=http://news.cnet.com/news/0-1003-200-2284759.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010413122744/http://news.cnet.com/news/0-1003-200-2284759.html |archive-date=2001-04-13 |date=July 18, 2000}}</ref> In March 2001 Intel said Itanium systems would begin shipping to customers in the second quarter, followed by a broader deployment in the second half of the year. By then even Intel publicly acknowledged that many customers would wait for McKinley.<ref>{{cite web |last1=Shankland |first1=Stephen |title=Intel draws out Itanium arrival |url=http://news.cnet.com/news/0-1003-200-4996738.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010413151817/http://news.cnet.com/news/0-1003-200-4996738.html |archive-date=2001-04-13 |date=1 March 2001}}</ref>
[[Image:Itanium Sales Forecasts edit.png|thumb|right|400px|Itanium Server Sales forecast history<ref name="IDC_chart">{{cite web
 | url=http://www.zdnet.com/pictures/charts-mining-itanium/
 | title=Mining Itanium
 | access-date=March 19, 2007
 | date=December 7, 2005
 | work=CNet News
 | archive-date=June 11, 2018
 | archive-url=https://web.archive.org/web/20180611040452/https://www.zdnet.com/pictures/charts-mining-itanium/
 | url-status=dead
 }}</ref><ref name="IDC 2006">{{cite news
 | url=https://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/
 | title=Analyst firm offers rosy view of Itanium
 | access-date=March 20, 2007
 | last=Shankland
 | first=Stephen
 | date=February 14, 2006
 | publisher=[[CNET|CNET News]]
 | archive-date=June 24, 2016
 | archive-url=https://web.archive.org/web/20160624090721/http://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/
 | url-status=live
 }}</ref>]]

==== Expectations ====
During development, Intel, HP, and industry analysts predicted that IA-64 would dominate first in 64-bit servers and workstations, then expand to the lower-end servers, supplanting Xeon, and finally penetrate into the [[personal computer]]s, eventually to supplant RISC and [[complex instruction set computing]] (CISC) architectures for all general-purpose applications, though not replacing x86 "for the foreseeable future" according to Intel.<ref>{{cite web |last1=Halfhill |first1=Tom R. |title=Beyond Pentium II |url=http://www.byte.com/art/9712/sec5/art1.htm |website=[[Byte (magazine)|Byte]] |archive-url=https://web.archive.org/web/20000302143120/http://www.byte.com/art/9712/sec5/art1.htm |archive-date=2000-03-02 |url-status=dead |date=December 1997}}</ref><ref name="nyt_merced"/><ref>{{cite web |last1=Connor |first1=Deni |title=Intel's Merced will coexist with 32-bit chips |url=https://books.google.com/books?id=AxwEAAAAMBAJ&pg=PA61 |website=[[Network World]] |date=1 March 1999}}</ref><ref>{{cite web |last1=Knorr |first1=Eric |title=Upgrading your server: A look at the Itanium |url=https://www.zdnet.com/article/upgrading-your-server-a-look-at-the-itanium/ |website=[[ZDNet]] |date=10 September 2001}}</ref><ref name="anand">{{cite web
 | url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598
 | title=Itanium–Is there light at the end of the tunnel?
 | access-date=March 23, 2007
 | last=De Gelas
 | first=Johan
 | date=November 9, 2005
 | work=[[AnandTech]]
 | archive-date=May 3, 2012
 | archive-url=https://web.archive.org/web/20120503094946/http://www.anandtech.com/show/1854
 | url-status=live
 }}</ref><ref name="Venturebeat">{{cite web
 | url=https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/
 | title=Exit interview: Retiring Intel chairman Craig Barrett on the industry's unfinished business
 | access-date=May 17, 2009
 | last=Takahashi
 | first=Dean
 | date=May 8, 2009
 | work=VentureBeat
 | archive-date=April 21, 2018
 | archive-url=https://web.archive.org/web/20180421095016/https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/
 | url-status=live
 }}</ref> In 1997-1998, Intel CEO [[Andy Grove]] predicted that Itanium would not come to the desktop computers for four of five years after launch, and said "I don't see Merced appearing on a mainstream desktop inside of a decade".<ref>{{cite web |last1=Nash |first1=Kim S. |title=Behind the Merced Mystique |url=https://books.google.com/books?id=03nTlQZ61IgC&pg=PT14 |website=[[Computerworld]] |date=6 July 1998}}</ref><ref name="nyt_merced"/> In contrast, Itanium was expected to capture 70% of the 64-bit server market in 2002.<ref>{{cite web |last1=Yu |first1=Elleen |title=IA-64 to overtake RISC |url=https://www.arnnet.com.au/article/110877/ia-64_overtake_risc/ |website=ARN |date=25 November 1998 |access-date=16 August 2022 |archive-date=29 January 2023 |archive-url=https://web.archive.org/web/20230129171855/https://www.arnnet.com.au/article/110877/ia-64_overtake_risc/ |url-status=dead }}</ref> Already in 1998 Itanium's focus on the high end of the computer market was criticized for making it vulnerable to challengers expanding from the lower-end market segments, but many people in the computer industry feared voicing doubts about Itanium in the fear of Intel's retaliation.<ref name="nyt_merced"/>
[[Compaq]] and [[Silicon Graphics]] decided to abandon further development of the [[DEC Alpha|Alpha]] and [[MIPS architecture|MIPS]] architectures respectively in favor of migrating to IA-64.<ref name="cautionary">{{cite web
 | url=https://www.zdnet.com/article/itanium-a-cautionary-tale/
 | title=Itanium: A cautionary tale
 | access-date=January 1, 2019
 | date=December 7, 2005
 | work=Tech News on ZDNet
 | archive-date=August 2, 2020
 | archive-url=https://web.archive.org/web/20200802000433/https://www.zdnet.com/article/itanium-a-cautionary-tale/
 | url-status=live
 }}</ref>

Several groups ported operating systems for the architecture, including [[Microsoft Windows]], [[OpenVMS]], [[Linux]], [[HP-UX]], [[Solaris (operating system)|Solaris]],<ref name="Solaris-Merced1">{{cite web
 | url=http://www.computerworld.com/home/news.nsf/all/9909013sunsol
 | title=Solaris for IA-64 coming this fall
 | last=Vijayan
 | first=Jaikumar
 | date=September 1, 1999
 | website=[[Computerworld]]
 | archive-date=January 15, 2000
 | archive-url=https://web.archive.org/web/20000115084746/http://www.computerworld.com/home/news.nsf/all/9909013sunsol
 | url-status=dead
 }}</ref><ref name="Solaris-Merced2">{{cite news |url=https://www.eetimes.com/core-logic-efforts-under-way-for-merced/ |title=Core-logic efforts under way for Merced |last=Wolfe |first=Alexander |access-date=December 17, 2019 |date=September 2, 1999 |magazine=[[EE Times]] |archive-date=December 17, 2019 |archive-url=https://web.archive.org/web/20191217201650/https://www.eetimes.com/core-logic-efforts-under-way-for-merced/ |url-status=live }}</ref><ref name="Solaris-Merced3">{{cite web
 | url=http://www.thefreelibrary.com/Sun+Introduces+Solaris+Developer+Kit+for+Intel+to+Speed+Development...-a020369933
 | title=Sun Introduces Solaris Developer Kit for Intel to Speed Development of Applications On Solaris; Award-winning Sun Tools Help ISVs Easily Develop for Solaris on Intel Today
 | access-date=June 6, 2016
 | date=March 10, 1998
 | work=Business Wire
 | quote=...developers can quickly develop applications today that will be compatible with and can easily be tuned for Solaris on Merced.
 | archive-date=August 5, 2016
 | archive-url=https://web.archive.org/web/20160805145446/http://www.thefreelibrary.com/Sun+Introduces+Solaris+Developer+Kit+for+Intel+to+Speed+Development...-a020369933
 | url-status=dead
 }}</ref>
[[Tru64 UNIX]],<ref name="cautionary"/> and [[Project Monterey|Monterey/64]].<ref>{{cite news
 | url=https://www.cnet.com/tech/tech-industry/next-generation-chip-passes-key-milestone/
 | title=Next-generation chip passes key milestone
 | last=Shankland
 | first=Stephen
 | date=September 17, 1999
 | publisher=[[CNET|CNET News]]
 }}</ref>
The latter three were canceled before reaching the market. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery timeframe of Merced began slipping.<ref name="may_slip"/>

Intel announced the official name of the processor, ''Itanium'', on October 4, 1999.<ref>{{cite web
 | url=https://www.cnet.com/tech/tech-industry/intel-names-merced-chip-itanium/
 | title=Intel names Merced chip Itanium
 | access-date=April 30, 2007
 | last=Kanellos
 | first=Michael
 | date=October 4, 1999
 | website=[[CNET]]
 }}</ref>
Within hours, the name '''''Itanic''''' had been coined on a [[Usenet]] newsgroup, a reference to the [[RMS Titanic|RMS ''Titanic'']], the "unsinkable" [[ocean liner]] that sank on her maiden voyage in 1912.<ref>{{cite newsgroup
 | url=https://groups.google.com/d/msg/comp.sys.mac.advocacy/UiOOaXF3-lI/f3nje9CHPx0J
 | title=Re:Itanium
 | access-date=May 20, 2020
 | last=Finstad
 | first=Kraig
 | date=October 4, 1999
 | newsgroup=comp.sys.mac.advocacy
 }}</ref> "Itanic" was then used often by ''[[The Register]]'',<ref name="Reg_Itanic">{{cite news
 | first=Pete
 | last=Sherriff
 | title=AMD vs Intel&nbsp;– our readers write
 | url=https://www.theregister.com/1999/10/28/amd_vs_intel_our_readers/
 | work=[[The Register]]
 | date=October 28, 1999
 | access-date=November 25, 2022
 }}</ref> and others,<ref>{{cite web
 |url          = https://www.zdnet.com/article/interpreting-mcnealys-lexicon/
 |title        = Interpreting McNealy's lexicon
 |access-date  = March 19, 2007
 |last         = Berlind
 |first        = David
 |date         = November 30, 2001
 |work         = [[ZDNet]] Tech Update
 |archive-date = September 4, 2019
 |archive-url  = https://web.archive.org/web/20190904215102/https://www.zdnet.com/article/interpreting-mcnealys-lexicon/
 |url-status   = live
}}</ref><ref>{{cite web
|url=http://www.theinquirer.net/inquirer/news/1004260/itanic-shell-game-continues
|url-status=unfit
|archive-url=https://web.archive.org/web/20160305085136/http://www.theinquirer.net/inquirer/news/1004260/itanic-shell-game-continues
|archive-date=March 5, 2016
|title=Itanic shell game continues
|access-date=February 27, 2016
|last=Demerjian
|first=Charlie
|date=July 18, 2006
|website=[[The Inquirer]]
}}</ref><ref>{{cite news|url=https://www.nytimes.com/2003/10/19/business/market-watch-fawning-analysts-betray-investors.html|title=Fawning Analysts Betray Investors|last=Morgenson|first=Gretchen|date=October 19, 2003|work=[[The New York Times]]|access-date=January 1, 2019|archive-date=October 11, 2012|archive-url=https://web.archive.org/web/20121011211448/http://www.zdnet.com/news/interpreting-mcnealys-lexicon/296322|url-status=live}}</ref> to imply that the multibillion-dollar investment in Itanium—and the early hype associated with it—would be followed by its relatively quick demise.

=== Itanium (Merced): 2001 ===
{{Infobox CPU
 | name=Itanium (Merced)
 | image=KL Intel Itanium ES.jpg
 | image_size=300px
 | caption=Itanium processor
 | produced-start=29 May–June 2001
 | produced-end=10 April 2003<ref>{{cite web |title=Product Change Notification |url=http://developer.intel.com/design/pcn/Processors/D0102840.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040719063719/http://developer.intel.com/design/pcn/Processors/D0102840.pdf |archive-date=2004-07-19}}</ref>
 | slowest=733
 | slow-unit=
 | fastest=800
 | fast-unit=MHz
 | fsb-slowest=266
 | fsb-slow-unit=MT/s
 | manuf1=Intel
 | core1=
 | size-from=
 | size-to=
 | arch=
 | sock1=[[PAC418]]
 | numcores=1
 | l2cache=96&nbsp;KB
 | l3cache=2 or 4&nbsp;MB
}}
After having sampled 40,000 chips to the partners, Intel launched Itanium on May 29, 2001, with first OEM systems from HP, IBM and Dell shipping to customers in June.<ref>{{cite web |last1=Niccolai |first1=James (IDG News Service) |title=Intel officially launches 64-bit Itanium chip |url=https://www.computerworld.com/article/2582076/intel-officially-launches-64-bit-itanium-chip.html |website=[[Computerworld]] |date=29 May 2001 |access-date=30 March 2022}}</ref><ref>{{cite web |title=Server makers tout Itanium models |url=https://www.zdnet.com/article/server-makers-tout-itanium-models-5000117490/ |website=[[ZDNet]] |access-date=30 March 2022}}</ref> By then Itanium's performance was not superior to competing RISC and CISC processors.<ref>{{cite magazine
 | author=Linley Gwennap
 | title=Itanium era dawns
 | url=https://www.eetimes.com/itanium-era-dawns/
 | magazine=EE Times
 | date=June 4, 2001
 | access-date=December 17, 2019
 | archive-date=December 17, 2019
 | archive-url=https://web.archive.org/web/20191217201629/https://www.eetimes.com/itanium-era-dawns/
 | url-status=live
 }}</ref>
Itanium competed at the low-end (primarily four-[[central processing unit|CPU]] and smaller systems) with servers based on [[x86]] processors, and at the high-end with [[IBM Power microprocessors|IBM POWER]] and [[Sun Microsystems]] [[SPARC]] processors. Intel repositioned Itanium to focus on the high-end business and [[High-performance computing|HPC]] computing markets, attempting to duplicate the x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing the [[PA-RISC]] in HP systems, [[DEC Alpha|Alpha]] in Compaq systems and [[MIPS architecture|MIPS]] in [[Silicon Graphics|SGI]] systems, though IBM also delivered a supercomputer based on this processor.<ref name="Thunder">{{cite web
 | url=http://www.top500.org/system/ranking/5597
 | title=Titan Cluster Itanium 800&nbsp;MHz
 | access-date=May 16, 2007
 | work=[[TOP500]] web site
 | archive-date=September 25, 2006
 | archive-url=https://web.archive.org/web/20060925041933/http://www.top500.org/system/ranking/5597
 | url-status=dead
 }}</ref>
POWER and SPARC remained strong, while the [[32-bit computing|32-bit]] x86 architecture continued to grow into the enterprise space, building on the economies of scale fueled by its enormous installed base.

Only a few thousand systems using the original ''Merced'' Itanium processor were sold, due to relatively poor performance, high cost and limited software availability.<ref>{{cite news
 | author=Michael Kanellos
 | title=Itanium sales off to a slow start
 | url=https://www.cnet.com/tech/tech-industry/itanium-sales-off-to-a-slow-start/
 | work=CNET News
 | date=December 11, 2001
 | access-date=July 4, 2023
 }}</ref> Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium&nbsp;2 processor to the market a year later. Few of the microarchitectural features of Merced would be carried over to all the subsequent Itanium designs, including the 16+16 KB L1 cache size and the 6-wide (two-bundle) instruction decoding.

=== Itanium 2 (McKinley and Madison): 2002–2006 ===
{{Infobox CPU
 | name=Itanium 2 (McKinley and Madison)
 | image=KL Intel Itanium2.jpg
 | image_size=300px
 | caption=Itanium 2 processor
 | produced-start=8 July 2002
 | produced-end=16 November 2007{{refn|McKinley: 16 April 2004<ref>{{cite web |title=Product Change Notification |url=http://developer.intel.com/design/pcn/Processors/D0103649.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040719080318/http://developer.intel.com/design/pcn/Processors/D0103649.pdf |archive-date=2004-07-19 |url-status=dead}}</ref><br/>Madison 6M: 28 July 2006<ref>{{cite web |title=Product Change Notification |url=http://developer.intel.com/design/pcn/Processors/D0105835.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20060313054448/http://developer.intel.com/design/pcn/Processors/D0105835.pdf |archive-date=2006-03-13 |url-status=dead}}</ref><br/>Madison 9M: 16 November 2007<ref>{{cite web |title=Product Change Notification |url=https://qdms.intel.com/dm/i.aspx/53B15559-69D6-4DD5-8379-0ABE33DCE8D4/PCN107564-00.pdf |publisher=Intel.<br/>Warning: forced download |access-date=28 April 2022}}</ref>}}
 | slowest=900
 | fastest=1667
 | slow-unit=
 | fast-unit=MHz
 | fsb-slowest=400
 | fsb-fastest=667
 | fsb-slow-unit=
 | fsb-fast-unit=MT/s
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[180 nm]]
 | size-to=[[130 nm]]
 | soldby=
 | designfirm=[[Hewlett-Packard|HP]] and Intel
 | manuf1=
 | core1=
 | sock1=[[PAC611]]
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=McKinley, Madison, Deerfield, Madison&nbsp;9M, Fanwood
 | numcores=1
 | l1cache=
 | l2cache=256&nbsp;KB
 | l3cache=1.5–9&nbsp;MB
 | application=
}}

The '''Itanium 2''' processor was released in July 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium&nbsp;2, code-named ''McKinley'', was jointly developed by HP and Intel, led by the HP team at [[Fort Collins, Colorado]], [[tape-out|taping out]] in December 2000. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem by approximately halving the latency and doubling the fill bandwidth of each of the three levels of cache, while expanding the L2 cache from 96 to 256 KB. Floating-point data is excluded from the L1 cache, because the L2 cache's higher bandwidth is more beneficial to typical floating-point applications than low latency. The L3 cache is now integrated on-chip rather than on a separate die, tripling in associativity and doubling in bus width.  McKinley also greatly increases the number of possible instruction combinations in a VLIW-bundle and reaches 25% higher frequency, despite having only eight pipeline stages versus Merced's ten.<ref>{{cite web |last1=Hammond |first1=Gary |last2=Naffziger |first2=Sam |title=Next Generation Itanium™ Processor Overview |url=http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-url=https://web.archive.org/web/20030706123550/http://intel.com/design/itanium2/download/McK-IDF-2001.pdf |archive-date=6 July 2003 |url-status=dead}}</ref><ref name="HP_McKinley_wp"/>

''McKinley'' contains 221 million transistors (of which 25 million are for logic and 181 million for L3 cache), measured 19.5&nbsp;mm by 21.6&nbsp;mm (421&nbsp;mm<sup>2</sup>) and was fabricated in a 180&nbsp;nm, bulk CMOS process with six layers of aluminium metallization.<ref>{{cite journal |last1=Naffzinger |first1=Samuel D. |first2=Glenn T. |last2=Colon-Bonet |first3=Timothy |last3=Fischer |first4=Reid |last4=Riedlinger |first5=Thomas J. |last5=Sullivan |first6=Tom |last6=Grutkowski |date=November 2002 |title=The implementation of the Itanium&nbsp;2 microprocessor |journal=[[IEEE Journal of Solid-State Circuits]] |volume=37 |issue=11 |pages=1448–1460 |doi=10.1109/JSSC.2002.803943 |bibcode=2002IJSSC..37.1448N |url=http://cpus.hp.com/technical_references/jssc_naffziger.pdf|archive-url=https://web.archive.org/web/20030322045555/http://cpus.hp.com/technical_references/jssc_naffziger.pdf |archive-date=2003-03-22 |url-status=dead}}</ref><ref>{{cite web |last1=Soltis |first1=Don |last2=Gibson |first2=Mark |title=Itanium® 2 Processor Microarchitecture Overview |url=http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |website=[[Hot Chips]] |archive-url=https://web.archive.org/web/20050531030015/http://www.hotchips.org/archives/hc14/2_Mon/03_soltis.pdf |archive-date=31 May 2005 |url-status=dead}}</ref><ref>{{cite web |last1=Naffziger |first1=Samuel |last2=Hammond |first2=Gary |title=The Implementation of the Next-Generation 64b Itanium Microprocessor |url=http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-url=https://web.archive.org/web/20041029174655/http://www.imec.be/elela/HD03/examens/2003/D20_6.pdf |archive-date=29 October 2004 |url-status=dead}}</ref> In May 2003 it was disclosed that some McKinley processors can suffer from a critical-path erratum leading to a system's crashing. It can be avoided by lowering the processor frequency to 800&nbsp;MHz.<ref>{{cite web |last1=Krazit |first1=Tom |title=Intel details Itanium 2 bug |url=https://www.computerworld.com/article/2570015/intel-details-itanium-2-bug.html |website=[[Computerworld]] |date=12 May 2003 |access-date=30 March 2022}}</ref>

In 2003, [[Advanced Micro Devices|AMD]] released the [[Opteron]] CPU, which implements its own [[64-bit computing|64-bit]] architecture called [[AMD64]]. The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from [[x86]]. Under the influence of Microsoft, Intel responded by implementing AMD's x86-64 [[instruction set architecture]] instead of IA-64 in its [[Xeon]] microprocessors in 2004, resulting in a new industry-wide ''de facto'' standard.<ref name="cautionary"/>

In 2003, Intel released a new Itanium&nbsp;2 family member, codenamed ''Madison'', initially with up to 1.5&nbsp;GHz frequency and 6 MB of L3 cache. The ''Madison 9M'' chip released in November 2004 had 9 MB of L3 cache and frequency up to 1.6&nbsp;GHz, reaching 1.67&nbsp;GHz in July 2005. Both chips used a 130&nbsp;nm process and were the basis of all new Itanium processors until Montecito was released in July 2006, specifically ''Deerfield'' being a low wattage ''Madison'', and ''Fanwood'' being a version of ''Madison 9M'' for lower-end servers with one or two CPU sockets.

In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate the software porting effort.<ref name="ISA">{{cite web
 |url          = http://www.itaniumsolutionsalliance.org
 |title        = Itanium Solutions Alliance
 |access-date   = May 16, 2007
 |work         = ISA web site
 |archive-url  = https://web.archive.org/web/20080908015727/http://www.itaniumsolutionsalliance.org/
 |archive-date = September 8, 2008
 |url-status   = usurped
 |df           = mdy-all
}}</ref>
The Alliance announced that its members would invest $10 billion in the Itanium Solutions Alliance by the end of the decade.<ref>{{cite web
 |url         = http://www.ednasia.com/article-12139-computingleadersannouncestrategyforneweraofmissioncriticalcomputing-Asia.html
 |title       = Computing Leaders Announce Strategy for New Era of Mission Critical Computing
 |access-date  = October 16, 2008
 |last        = Scott
 |first       = Bilepo
 |date        = January 26, 2006
 |work        = Itanium Solutions Alliance Press Release
 |archive-url  = https://web.archive.org/web/20120111011444/http://www.ednasia.com/article-12139-computingleadersannouncestrategyforneweraofmissioncriticalcomputing-Asia.html
 |archive-date = January 11, 2012
 |url-status  = dead
 |df          = mdy-all
}}</ref>

=== Itanium 2 9000 and Itanium 9100: 2006 and 2007 ===
{{Infobox CPU
 | name=9000 and 9100 series
 | image=Intel Itanium 2 9000 with cap removed.jpg
 | image_size=300px
 | caption=Intel Itanium&nbsp;2 9000 ([[heat spreader]] [[Decapping|removed]])
 | produced-start=18 July 2006
 | produced-end=26 August 2011<ref>{{cite web |title=Intel server processors to be discontinued in 2012 |url=https://www.cpu-world.com/news_2011/2011021601_Intel_server_processors_to_be_discontinued_in_2012.html |website=CPU-World |access-date=28 April 2022}}</ref>
 | slowest=1.4
 | fastest=1.67
 | fast-unit=GHz
 | fsb-slowest=400
 | fsb-fastest=667
 | fsb-slow-unit=
 | fsb-fast-unit=MT/s
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[90 nm]]
 | size-to=
 | soldby=
 | designfirm=
 | manuf1=
 | core1=
 | sock1=[[PAC611]]
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=Montecito, Montvale
 | numcores=1 or 2
 | l1cache=
 | l2cache=256&nbsp;KB&nbsp;(D) + 1&nbsp;MB&nbsp;(I)
 | l3cache=6–24&nbsp;MB
 | application=
}}
{{Main|Montecito (processor)}}
In early 2003, due to the success of IBM's dual-core [[POWER4]], Intel announced that the first [[90 nm]] Itanium processor, codenamed ''Montecito'', would be delayed to 2005 so as to change it into a dual-core, thus merging it with the ''Chivano'' project.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel accelerates Itanium schedule |url=https://www.cnet.com/tech/tech-industry/intel-accelerates-itanium-schedule/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref name="qa">{{cite news |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel's summer of servers |url=https://www.theglobeandmail.com/technology/intels-summer-of-servers/article1163609/ |website=[[The Globe and Mail]] |date=9 July 2003 |access-date=27 April 2022}}</ref> In September 2004 Intel demonstrated a working Montecito system, and claimed that the inclusion of [[hyper-threading]] increases Montecito's performance by 10-20% and that its frequency could reach 2&nbsp;GHz.<ref name="monty">{{cite web |last1=Kanellos |first1=Michael |title=Intel fills in more details on Itanium family |url=https://www.cnet.com/tech/tech-industry/intel-fills-in-more-details-on-itanium-family/ |website=[[CNET]] |access-date=3 April 2022}}</ref><ref>{{cite web |last1=Wilson |first1=Derek |title=Intel Developer Forum Fall 2004: Day 1 Keynote |url=https://www.anandtech.com/show/1465/3 |website=[[AnandTech]] |access-date=28 April 2022}}</ref> After a delay to "mid-2006" and reduction of the frequency to 1.6&nbsp;GHz,<ref>{{cite news |last1=Shankland |first1=Stephen |title=Intel pushes back Itanium chips, revamps Xeon |url=https://www.cnet.com/tech/tech-industry/intel-pushes-back-itanium-chips-revamps-xeon/ |website=[[CNET]] |access-date=3 April 2022}}</ref> on July 18 Intel delivered ''Montecito'' (marketed as the '''Itanium&nbsp;2 9000''' series), a [[multi-core processor|dual-core]] processor with a [[Multithreading (computer architecture)#Coarse-grained multithreading|switch-on-event multithreading]] and split 256 KB + 1 MB L2 caches that roughly doubled the performance and decreased the energy consumption by about 20 percent.<ref name="CW1">{{cite web
 |url          = https://www.computerworld.com/article/2536018/-tukwila--itanium-servers-due-early-next-year--intel-says.html
 |title        = 'Tukwila' Itanium servers due early next year, Intel says
 |access-date  = September 26, 2022
 |last         = Niccolai
 |first        = James
 |date         = May 20, 2008
 |work         = [[Computerworld]]
}}</ref> At 596&nbsp;mm² die size and 1.72 billion transistors it was the largest microprocessor at the time. It was supposed to feature [[Foxton Technology]], a very sophisticated frequency regulator, which failed to pass validation and was thus not enabled for customers.

Intel released the '''Itanium 9100''' series, codenamed ''Montvale'', in November 2007, retiring the "Itanium 2" brand.<ref name="IW1">{{cite web
 | url=http://www.informationweek.com/story/showArticle.jhtml?articleID=202800983
 | title=Intel Unveils Seven Itanium Processors
 | access-date=November 6, 2007
 | last=Gonsalves
 | first=Antone
 | date=November 1, 2007
 | work=[[InformationWeek]]
 | archive-date=March 10, 2012
 | archive-url=https://web.archive.org/web/20120310003352/http://www.informationweek.com/
 | url-status=dead
 }}</ref> Originally intended to use the [[65 nm process]],<ref name="idf04f">{{cite web |title=Intel Shares Findings, Platform Plans To Better Guide Businesses Through 'Transformation' |url=https://www.intel.com/pressroom/archive/releases/2004/20040907corp_a.htm |publisher=Intel}}</ref> it was changed into a fix of Montecito, enabling the demand-based switching (like [[EIST]]) and up to 667 MT/s [[front-side bus]], which were intended for Montecito, plus a core-level [[Lockstep (computing)|lockstep]].<ref name="monty"/> Montecito and Montvale were the last Itanium processors in which design [[Hewlett-Packard]]'s engineering team at Fort Collins had a key role, as the team was subsequently transferred to Intel's ownership.<ref>{{cite web |title=Intel Strengthens Investment In Intel® Itanium® Architecture With Hiring Of HP Design Team |url=https://www.intel.com/pressroom/archive/releases/2004/20041216comp.htm}}</ref>

=== Itanium 9300 (Tukwila): 2010 ===
{{Infobox CPU
 | name=9300 series
 | produced-start=8 February 2010
 | produced-end=2nd quarter of 2014
 | slowest=1.33
 | fastest=1.73
 | slow-unit=
 | fast-unit=GHz
 | fsb-slowest=
 | fsb-fastest=
 | fsb-slow-unit=
 | fsb-fast-unit=
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[65 nm]]
 | size-to=
 | soldby=
 | designfirm=
 | manuf1=
 | sock1=FC-LGA6 ([[LGA1248]])
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=
 | numcores=2 or 4
 | l1cache=
 | l2cache=256&nbsp;KB&nbsp;(D) + 512&nbsp;KB&nbsp;(I)
 | l3cache=10–24&nbsp;MB
 | application=
}}
{{Infobox CPU
 | name=9500 and 9700 series
 | produced-start=8 November 2012
 | produced-end=30 January 2020<ref>{{cite web |last1=Shilov |first1=Anton |title=Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums |url=https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |website=[[AnandTech]] |access-date=28 April 2022}}</ref>
 | slowest=1.73
 | fastest=2.67
 | slow-unit=
 | fast-unit=GHz
 | fsb-slowest=
 | fsb-fastest=
 | fsb-slow-unit=
 | fsb-fast-unit=
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[32 nm]]
 | size-to=
 | soldby=
 | designfirm=
 | manuf1=
 | sock1=FC-LGA6 ([[LGA1248]])
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=Poulson, Kittson
 | numcores=4 or 8
 | l1cache=
 | l2cache=256&nbsp;KB&nbsp;(D) + 512&nbsp;KB&nbsp;(I)
 | l3cache=20–32&nbsp;MB
 | application=
}}
[[File:Intel Itanium 9300 CPU Top with cap.png|thumb|Intel Itanium 9300 CPU]]
[[File:Intel Itanium 9300 CPU bottom.png|thumb|Intel Itanium 9300 CPU LGA]]
[[File:Intel Itanium 9300 Socket Intel LGA 1248.JPG|thumb|Intel Itanium 9300 Socket Intel LGA 1248]]
[[File:Intel Itanium 9300 with cap removed.jpg|thumb|Intel Itanium 9300 with cap removed]]
{{Main|Tukwila (processor)|}}
The original code name for the first Itanium with more than two cores was Tanglewood, but it was changed to Tukwila in late 2003 due to trademark issues.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel changes code name of future Itanium |url=https://www.cnet.com/tech/tech-industry/intel-changes-code-name-of-future-itanium/ |website=[[CNET]] |access-date=4 July 2023}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Trademark flap prompts Intel to rename Tanglewood |url=https://www.infoworld.com/article/2678103/trademark-flap-prompts-intel-to-rename-tanglewood.html |website=[[InfoWorld]] |date=18 December 2003 |access-date=31 March 2022}}</ref> Intel discussed a "middle-of-the-decade Itanium" to succeed Montecito, achieving ten times the performance of Madison.<ref>{{cite news |last1=Vance |first1=Ashlee |author-link=Ashlee Vance |title=Tanglewood to run 10x faster than Madison |url=https://www.theregister.com/2003/05/01/tanglewood_to_run_10x_faster1/ |work=[[The Register]] |access-date=27 April 2022}}</ref><ref name="qa"/> It was being designed by the famed [[DEC Alpha]] team and was expected have eight new multithreading-focused cores. Intel claimed "a lot more than two" cores and more than seven times the performance of Madison.<ref>{{cite web |last1=McMillan |first1=Robert |title=FALL IDF: Intel readies 8-core, 16-core Itanium 2 |url=https://www.infoworld.com/article/2676169/fall-idf--intel-readies-8-core--16-core-itanium-2.html |website=[[InfoWorld]] |date=17 September 2003 |access-date=31 March 2022}}</ref><ref>{{cite web |last1=Shankland |first1=Stephen |title='Tanglewood' to top Intel chip show |url=https://www.cnet.com/tech/tech-industry/tanglewood-to-top-intel-chip-show/ |website=[[CNET]] |access-date=31 March 2022}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Itanium 2 Montecito to be multithreaded |url=https://www.computerweekly.com/news/2240053525/Itanium-2-Montecito-to-be-multithreaded |website=[[Computer Weekly]] |access-date=31 March 2022}}</ref> In early 2004 Intel told of "plans to achieve up to double the performance over the Intel Xeon processor family at platform cost parity by 2007".<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel}}</ref> By early 2005 Tukwila was redefined, now having fewer cores but focusing on single-threaded performance and multiprocessor scalability.<ref>{{cite web |last1=Shankland |first1=Stephen |title=Intel to spotlight new Itanium: 'Poulson' |url=https://www.cnet.com/tech/tech-industry/intel-to-spotlight-new-itanium-poulson/ |website=[[CNET]] |access-date=31 March 2022}}</ref>

In March 2005, Intel disclosed some details of Tukwila, the next Itanium processor after Montvale, to be released in 2007. Tukwila would have [[multi-core processor|four processor cores]] and would replace the Itanium bus with a new [[Common System Interface]], which would also be used by a new Xeon processor.<ref name="CSI">{{cite magazine
 |url          = https://www.eetimes.com/intel-preps-hypertransport-competitor-for-xeon-itanium-cpus/
 |title        = Intel preps HyperTransport competitor for Xeon, Itanium CPUs
 |access-date  = December 17, 2019
 |last         = Merritt
 |first        = Rick
 |date         = March 2, 2005
 |magazine     = EE Times
 |archive-date = December 17, 2019
 |archive-url  = https://web.archive.org/web/20191217201715/https://www.eetimes.com/intel-preps-hypertransport-competitor-for-xeon-itanium-cpus/
 |url-status   = live
}}</ref> Tukwila was to have a "common platform architecture" with a Xeon codenamed ''Whitefield'',<ref name="idf04f"/> which was canceled in October 2005,<ref>{{cite news |last1=Vance |first1=Ashlee |author-link=Ashlee Vance |title=Intel's Xeon chip kill is result of chaos in India |url=https://www.theregister.com/2005/10/28/intel_whitefield_india/ |work=[[The Register]] |access-date=28 April 2022}}</ref> when Intel revised Tukwila's delivery date to late 2008.<ref name="zdnet_2005_slip">{{cite web
 | url=https://www.zdnet.com/article/intel-pushes-back-itanium-chips-revamps-xeon/
 | title=Intel pushes back Itanium chips, revamps Xeon
 | access-date=January 1, 2019
 | last=Shankland
 | first=Stephen
 | date=October 24, 2005
 | work=[[ZDNet]] News
 | archive-date=August 2, 2020
 | archive-url=https://web.archive.org/web/20200802000438/https://www.zdnet.com/article/intel-pushes-back-itanium-chips-revamps-xeon/
 | url-status=live
 }}</ref> In May 2009, the schedule for Tukwila, was revised again, with the release to OEMs planned for the first quarter of 2010.<ref name="INQ09">{{cite web
 | url=http://www.theinquirer.net/inquirer/news/1137434/tukwila-delayed-2010
 | title=Tukwila delayed until 2010
 | access-date=May 21, 2009
 | last=Demerjian
 | first=Charlie
 | date=May 21, 2009
 | website=[[The Inquirer]]
 | url-status=unfit
 | archive-url=https://web.archive.org/web/20090523101543/http://www.theinquirer.net/inquirer/news/1137434/tukwila-delayed-2010
 | archive-date=May 23, 2009
}}</ref>
The '''Itanium 9300''' series processor, codenamed ''Tukwila'', was released on February 8, 2010, with greater performance and memory capacity.<ref name="eweek-tukwila">{{cite web|url=https://www.eweek.com/networking/new-intel-itanium-offers-greater-performance-memory-capacity/|title=New Intel Itanium Offers Greater Performance, Memory Capacity|first=Jeff|last=Burt|date=February 8, 2010|website=[[eWeek]]}}</ref>

The device uses a 65&nbsp;nm process, includes two to four cores, up to 24&nbsp;[[Mebibyte|MB]] on-die caches, [[Hyper-Threading]] technology and integrated memory controllers. It implements [[ECC memory|double-device data correction]], which helps to fix memory errors. Tukwila also implements [[Intel QuickPath Interconnect]] (QPI) to replace the Itanium bus-based architecture. It has a peak interprocessor bandwidth of 96&nbsp;GB/s and a peak memory bandwidth of 34&nbsp;GB/s. With QuickPath, the processor has integrated memory controllers and interfaces the memory directly, using QPI interfaces to directly connect to other processors and I/O hubs. QuickPath is also used on Intel [[x86-64]] processors using the ''[[Nehalem (microarchitecture)|Nehalem]]'' microarchitecture, which possibly enabled Tukwila and Nehalem to use the same chipsets.<ref name="Kittson">{{cite web
 | url=https://www.zdnet.com/article/intel-updates-itanium-line-with-kittson/
 | title=Intel updates Itanium line with 'Kittson'
 | access-date=June 15, 2007
 | last=Tan
 | first=Aaron
 | date=June 15, 2007
 | work=[[ZDNet]]
 }}</ref>
Tukwila incorporates two memory controllers, each of which has two links to Scalable Memory Buffers, which in turn support multiple [[DDR3 SDRAM|DDR3]] [[DIMM]]s,<ref name=TukwilaDelay>{{cite web
 | url=https://arstechnica.com/business/news/2009/02/intel-delays-quad-itanium-to-boost-platform-memory-capacity.ars
 | title=Intel delays quad Itanium to boost platform memory capacity
 | access-date=February 5, 2009
 | last=Stokes
 | first=Jon
 | date=February 5, 2009
 | work=ars technica
 | archive-date=January 22, 2012
 | archive-url=https://web.archive.org/web/20120122093011/http://arstechnica.com/business/news/2009/02/intel-delays-quad-itanium-to-boost-platform-memory-capacity.ars
 | url-status=live
 }}</ref>
much like the Nehalem-based Xeon processor code-named ''[[Beckton (microprocessor)|Beckton]]''.<ref name="DailyTech Server">{{cite news
 |url          = http://www.dailytech.com/Intel+Aims+for+Efficiency+With+New+Server+Roadmap/article14224.htm
 |first        = Jansen
 |last         = Ng
 |title        = Intel Aims for Efficiency With New Server Roadmap
 |date         = February 10, 2009
 |work    = [[DailyTech]]
 |access-date   = February 10, 2009
 |archive-url  = https://web.archive.org/web/20090213150005/http://www.dailytech.com/intel+aims+for+efficiency+with+new+server+roadmap/article14224.htm
 |archive-date = February 13, 2009
 |url-status   = dead
 |df           = mdy-all
}}</ref>

=== ''HP vs. Oracle'' ===
During the 2012 ''Hewlett-Packard Co. v. Oracle Corp.'' support lawsuit, court documents unsealed by a Santa Clara County Court judge revealed that in 2008, Hewlett-Packard had paid Intel around $440 million to keep producing and updating Itanium microprocessors from 2009 to 2014. In 2010, the two companies signed another $250 million deal, which obliged Intel to continue making Itanium CPUs for HP's machines until 2017. Under the terms of the agreements, HP had to pay for chips it gets from Intel, while Intel launches Tukwila, Poulson, Kittson, and Kittson+ chips in a bid to gradually boost performance of the platform.<ref>{{cite web|url=http://www.xbitlabs.com/news/cpu/display/20120201201109_HP_Paid_Intel_690_Million_to_Keep_Itanium_Alive_Court_Findings.html|title=HP Paid Intel $690 Million to Keep Itanium Alive - Court Findings.|archive-url=https://web.archive.org/web/20160304054256/http://www.xbitlabs.com/news/cpu/display/20120201201109_HP_Paid_Intel_690_Million_to_Keep_Itanium_Alive_Court_Findings.html|archive-date=March 4, 2016|url-status=dead}}</ref><ref>{{cite magazine|url=https://www.wired.com/wiredenterprise/2012/02/hp-itanium/|title=HP Paid Intel $690 Million To Keep Itanium On Life Support|author=Robert McMillan|date=February 1, 2012|magazine=[[Wired (magazine)|Wired]]|access-date=March 7, 2017|archive-date=March 6, 2014|archive-url=https://web.archive.org/web/20140306014953/http://www.wired.com/wiredenterprise/2012/02/hp-itanium/|url-status=live}}</ref>

=== Itanium 9500 (Poulson): 2012 ===
Intel first mentioned Poulson on March 1, 2005, at the Spring [[Intel Developer Forum|IDF]].<ref>{{cite web |title=Intel Platforms, Technologies To Drive Enterprise Advances |url=https://www.intel.com/pressroom/archive/releases/2005/20050301corp_a.htm |publisher=Intel |access-date=31 March 2022}}</ref> In June 2007 Intel said that Poulson would use a [[32 nanometer|32&nbsp;nm]] process technology, skipping the [[45 nanometer|45&nbsp;nm]] process.<ref name="mercury"/> This was necessary for catching up after Itanium's delays left it at [[90 nm]] competing against [[65 nm]] and [[45 nm]] processors.

At [[International Solid-State Circuits Conference|ISSCC]] 2011, Intel presented a paper called "A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium Processor for Mission Critical Servers."<ref name="dx.doi.org"/><ref>{{cite web
 |url         = http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf
 |title         = ISSCC 2011
 |access-date         = November 17, 2017
 |archive-date         = December 1, 2017
 |archive-url         = https://web.archive.org/web/20171201034615/http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf
 |url-status  = dead
 }}</ref>
Analyst David Kanter speculated that Poulson would use a new microarchitecture, with a more advanced form of multithreading that uses up to two threads, to improve performance for single threaded and multithreaded workloads.<ref>{{cite web
 | url=https://www.realworldtech.com/poulson-preview/
 | title=New Itanium Microarchitecture at ISSCC 2011
 | access-date=July 4, 2023
 | last=Kanter
 | first=David
 | date=November 17, 2010
 | work=Real World Tech
 }}</ref>
Some information was also released at the [[Hot Chips]] conference.<ref>{{cite web
 |url         = https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/
 |title         = Itanium Poulson Update&nbsp;— Greater Parallelism, New Instruction Replay & More: Catch the details from Hotchips!
 |date         = August 19, 2011
 |access-date         = November 17, 2017
 |archive-date         = June 27, 2018
 |archive-url         = https://web.archive.org/web/20180627144340/https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/
 |url-status         = live
 }}</ref><ref>{{cite web
 | url=http://www.slideshare.net/PaulineNist/intel-itanium-poulson-update-at-hotchips
 | title=Intel Itanium Hotchips 2011 Overview
 | date=18 August 2011
 | access-date=January 23, 2012
 | archive-date=14 February 2012
 | archive-url=https://web.archive.org/web/20120214131459/http://www.slideshare.net/PaulineNist/intel-itanium-poulson-update-at-hotchips
 | url-status=live
 }}</ref>

Information presented improvements in multithreading, resiliency improvements ([[Intel Instruction Replay]] RAS) and few new instructions (thread priority, integer instruction, cache prefetching, and data access hints).

Poulson was released on November 8, 2012, as the '''Itanium 9500''' series processor. It is the follow-on processor to Tukwila. It features eight cores and has a 12-wide issue architecture, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization.<ref name="Kittson"/><ref name="poulson-the-future-of-itanium-servers">{{cite web
 | url=https://www.realworldtech.com/poulson/
 | last=Kanter
 | first=David
 | title=Poulson: The Future of Itanium Servers
 | publisher=Real World Tech
 | date=May 18, 2011
 | access-date=November 9, 2012
 | archive-url=https://web.archive.org/web/20121102093620/http://www.realworldtech.com/poulson/
 | archive-date=November 2, 2012
 | url-status=live
 }}</ref><ref name="HotChip-Poulson">{{cite web
 |url         = http://newsroom.intel.com/servlet/JiveServlet/download/38-5835/Hot%20Chips%20%20Poulson%20disclosure%20Factsheet.pdf
 |title       = Hot Chips Poulson Disclosure Factsheet
 |access-date  = August 19, 2011
 |date        = August 19, 2011
 |work        = Intel press release
 |archive-url  = https://web.archive.org/web/20120324101540/http://newsroom.intel.com/servlet/JiveServlet/download/38-5835/Hot%20Chips%20%20Poulson%20disclosure%20Factsheet.pdf
 |archive-date = March 24, 2012
 |url-status  = dead
 |df          = mdy-all
}}</ref>
The Poulson L3 cache size is 32&nbsp;MB and common for all cores, not divided like previously. L2 cache size is 6&nbsp;MB, 512&nbsp;I&nbsp;[[Kibibyte|KB]], 256&nbsp;D&nbsp;KB per core.<ref name="dx.doi.org">{{cite conference
 | chapter=A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers
 | date=February 24, 2011
 |doi = 10.1109/ISSCC.2011.5746230|conference = 2011 IEEE International Solid-State Circuits Conference|pages = 84–86|last1 = Riedlinger|first1 = Reid J.|last2 = Bhatia|first2 = Rohit|last3 = Biro|first3 = Larry|last4 = Bowhill|first4 = Bill|last5 = Fetzer|first5 = Eric|last6 = Gronowski|first6 = Paul|last7 = Grutkowski|first7 = Tom| title=2011 IEEE International Solid-State Circuits Conference
 |isbn = 978-1-61284-303-2}}</ref> Die size is 544&nbsp;mm², less than its predecessor Tukwila (698.75&nbsp;mm²).<ref>{{cite magazine
 | url=https://www.eetimes.com/researchers-carve-cpu-into-plastic-foil/
 | title=Researchers carve CPU into plastic foil
 | first=Rick
 | last=Merrit
 | date=November 23, 2010
 | magazine=EE Times
 | access-date=December 17, 2019
 | archive-date=December 17, 2019
 | archive-url=https://web.archive.org/web/20191217201623/https://www.eetimes.com/researchers-carve-cpu-into-plastic-foil/
 | url-status=live
 }}</ref><ref>{{cite web
 | url=https://www.engadget.com/2011/08/22/intel-talks-up-next-gen-itanium-32nm-8-core-poulson/
 | title=Intel talks up next-gen Itanium: 32nm, 8-core Poulson
 | first=Terrence
 | last=O'Brien
 | publisher=[[Engadget]]
 | date=August 22, 2011
 | access-date=April 30, 2012
 | archive-date=April 21, 2018
 | archive-url=https://web.archive.org/web/20180421163456/https://www.engadget.com/2011/08/22/intel-talks-up-next-gen-itanium-32nm-8-core-poulson/
 | url-status=live
 }}</ref>

Intel's Product Change Notification (PCN) 111456-01 lists four models of Itanium 9500 series [[central processing unit|CPU]], which was later removed in a revised document.<ref name="cpu-world.com">{{cite web| url = http://www.cpu-world.com/news_2012/2012061301_Unreleased_Intel_Itanium_9500-series_CPUs_spotted.html| title = Unreleased Intel Itanium 9500-series CPUs spotted| access-date = 2012-08-02| archive-date = 2017-11-22| archive-url = https://web.archive.org/web/20171122032035/http://www.cpu-world.com/news_2012/2012061301_Unreleased_Intel_Itanium_9500-series_CPUs_spotted.html| url-status = live}}</ref> The parts were later listed in Intel's Material Declaration Data Sheets (MDDS) database.<ref>{{cite web| url = http://www.cpu-world.com/news_2012/2012062601_Spotted_9500-series_CPUs_confirmed_to_be_Poulson_Itaniums.html| title = Spotted 9500-series CPUs confirmed to be "Poulson" Itaniums| access-date = 2012-08-02| archive-date = 2017-10-06| archive-url = https://web.archive.org/web/20171006152039/http://www.cpu-world.com/news_2012/2012062601_Spotted_9500-series_CPUs_confirmed_to_be_Poulson_Itaniums.html| url-status = live}}</ref> Intel later posted Itanium 9500 reference manual.<ref>{{cite web| url = http://www.cpu-world.com/news_2012/2012071101_Intel_publishes_Itanium_9500_reference_manual.html| title = Intel publishes Itanium 9500 reference manual| access-date = 2012-08-02| archive-date = 2017-10-08| archive-url = https://web.archive.org/web/20171008075849/http://www.cpu-world.com/news_2012/2012071101_Intel_publishes_Itanium_9500_reference_manual.html| url-status = live}}</ref>

The models are the following:<ref name="cpu-world.com"/><ref>{{cite web|title=Products formerly Poulson|url=http://ark.intel.com/products/codename/26643/Poulson|website=Intel® ARK (Product Specs)|access-date=May 31, 2017|archive-date=May 18, 2017|archive-url=https://web.archive.org/web/20170518065154/http://ark.intel.com/products/codename/26643/Poulson|url-status=live}}</ref>
:{| class="wikitable"
|-
!Processor number||Frequency||Cache
|-
|9520||1.73&nbsp;GHz||20MB
|-
|9540||2.13&nbsp;GHz||24MB
|-
|9550||2.40&nbsp;GHz||32MB
|-
|9560||2.53&nbsp;GHz||32MB
|}

=== Itanium 9700 (Kittson): 2017 ===
Intel had committed to at least one more generation after Poulson, first mentioning Kittson on 14 June 2007.<ref name="mercury">{{cite web |last1=Boslet |first1=Mark |title=Intel to employ advanced technology on server chips |url=https://www.mercurynews.com/2007/06/14/intel-to-employ-advanced-technology-on-server-chips/ |website=[[The Mercury News]] |date=15 June 2007 |access-date=26 February 2022}}</ref> Kittson was supposed to be on a 22&nbsp;nm process and use the same [[LGA2011]] socket and platform as [[Xeon]]s.<ref>{{cite web |last1=Wheeler |first1=Bob |title=Tocking Itanium |url=https://www.linleygroup.com/newsletters/newsletter_detail.php?num=4912 |publisher=[[Microprocessor Report|The Linley Group]] |access-date=26 February 2022}}</ref><ref>{{cite web |last1=Skaugen |first1=Kirk |title=IDF2011 Intel Developer Forum |url=https://download.intel.com/newsroom/kits/idf/2011_fall/pdfs/Kirk_Skaugen_DCSG_MegaBriefing.pdf |publisher=slide 21. Intel |access-date=26 February 2022}}</ref><ref>{{cite web |last1=Nist |first1=Pauline |title=More than just another Itanium chip |url=https://itpeernetwork.intel.com/more-than-just-another-itanium-chip/#gs.r3sxvd |publisher=Intel |access-date=26 February 2022 |archive-url=https://web.archive.org/web/20200808053527/https://itpeernetwork.intel.com/more-than-just-another-itanium-chip/#gs.r3sxvd |archive-date=8 August 2020 |url-status=dead}}</ref> On 31 January 2013 Intel issued an update to their plans for Kittson: it would have the same [[LGA1248]] socket and 32&nbsp;nm process as Poulson, thus effectively halting any further development of Itanium processors.<ref>{{cite web |title=Intel® Itanium® Processors Update |url=http://www.intel.com/content/www/us/en/processors/itanium/itanium-kittson-update.html |archive-url=https://web.archive.org/web/20161109135111/http://www.intel.com/content/www/us/en/processors/itanium/itanium-kittson-update.html |archive-date=9 November 2016 |url-status=dead}}</ref>

In April 2015, Intel, although it had not yet confirmed formal specifications, did confirm that it continued to work on the project.<ref name=kitguru>{{cite web |url=https://www.kitguru.net/components/cpu/anton-shilov/intel-still-committed-to-make-new-itanium-processors/ |title=Intel still committed to make new Itanium processors |quote=KitGuru Says: Even though it is highly likely that "Kittson" chips will be released, it does not seem that Intel and HP actually want to invest R&D money in boosting performance of IA-64 chips. As a result, it looks like the best thing "Kittson" will offer will be a 20 per cent performance improvement over current gen offerings. |last1=Shilov |first1=Anton |date=April 17, 2015 |website=kitguru.net |access-date=July 4, 2023}}</ref> Meanwhile, the aggressively multicore Xeon E7 platform displaced Itanium-based solutions in the Intel roadmap.<ref>{{cite web |url=http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html |title=Intel's new Xeon server chip pushes Itanium closer to death's door |last1=Shah |first1=Agam |date=February 19, 2014 |website=pcworld.com |publisher=PC World |access-date=January 13, 2016 |archive-date=January 26, 2016 |archive-url=https://web.archive.org/web/20160126165249/http://www.pcworld.com/article/2099260/intels-new-xeon-server-chip-pushes-itanium-closer-to-end.html |url-status=live }}</ref> Even [[Hewlett-Packard]], the main proponent and customer for Itanium, began selling [[x86]]-based [[HP Superdome|Superdome]] and [[NonStop (server computers)|NonStop]] servers, and started to treat the Itanium-based versions as legacy products.<ref>{{cite web |last1=Shilov |first1=Anton |title=HP: mission-critical servers business improves as Itanium fades away |url=https://www.kitguru.net/professional/server/anton-shilov/hp-mission-critical-servers-business-improves-as-itanium-fades-away/ |website=Kitguru |access-date=30 March 2022}}</ref><ref>{{cite web |last1=Shah |first1=Agam |title=HP sees HP-UX sticking around for 10 years |url=https://www.computerworld.com/article/2853998/hp-sees-hp-ux-sticking-around-for-10-years.html |website=[[Computerworld]] |date=2 December 2014 |access-date=30 March 2022}}</ref>

Intel officially launched the '''Itanium 9700''' series processor family on May 11, 2017.<ref>{{cite web|title=Intel® Itanium® Processor|url=https://www-ssl.intel.com/content/www/us/en/products/processors/itanium.html|website=Intel|access-date=May 15, 2017}}</ref><ref name="IA-PCWorld"/> Kittson has no microarchitecture improvements over Poulson; despite nominally having a different stepping, it is functionally identical with the 9500 series, even having exactly the same bugs, the only difference being the 133&nbsp;MHz higher frequency of 9760 and 9750 over 9560 and 9550 respectively.<ref>{{cite web |title=Intel® Itanium® Processor 9300, 9500 and 9700 Series Specification Update |url=https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20201111234308/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/9300-9500-9700-series-spec-update.pdf |archive-date=11 November 2020 |url-status=live}}</ref><ref>{{cite news|last1=Cutress|first1=Ian|title=Intel's Itanium Takes One Last Breath: Itanium 9700 Series CPUs Released|url=http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|access-date=May 11, 2017|publisher=Anandtech|date=May 11, 2017|archive-date=May 11, 2017|archive-url=https://web.archive.org/web/20170511152533/http://www.anandtech.com/show/11372/intels-itanium-takes-one-last-breath-9700-series-released|url-status=live}}</ref>

Intel announced that the 9700 series would be the last Itanium chips produced.<ref name="Davis 2017" /><ref name="IA-PCWorld" />

The models are:<ref>{{cite web|title=Products formerly Kittson|url=https://ark.intel.com/content/www/us/en/ark/products/codename/32203/kittson.html|website=Intel® ARK (Product Specs)|access-date=May 15, 2017|archive-date=August 4, 2019|archive-url=https://web.archive.org/web/20190804134312/https://ark.intel.com/content/www/us/en/ark/products/codename/32203/kittson.html|url-status=live}}</ref>
:{| class="wikitable sortable"
|-
!Processor number||Cores||Threads||Frequency||Cache
|-
|9720||4||{{0}}8||1.73&nbsp;GHz||20&nbsp;MB
|-
|9740||8||16||2.13&nbsp;GHz||24&nbsp;MB
|-
|9750||4||{{0}}8||2.53&nbsp;GHz||32&nbsp;MB
|-
|9760||8||16||2.66&nbsp;GHz||32&nbsp;MB
|}