Editing JTAG (section)

== History ==
In the 1980s, multi-layer circuit boards and [[integrated circuit]]s (ICs) using [[ball grid array]] and similar mounting technologies were becoming standard, and connections were being made between ICs that were not available to probes. The majority of manufacturing and field faults in circuit boards were due to poor [[solder]] joints on the boards, imperfections among board connections, or the bonds and bond wires from IC pads to pin lead frames. The Joint Test Action Group (JTAG) was formed in 1985 to provide a pins-out view from one IC pad to another so these faults could be discovered.

The industry standard became an [[IEEE]] standard in 1990 as IEEE Std. 1149.1-1990<ref name="ieee1149.1-1990">Copies of [https://archive.today/20130415041034/http://standards.ieee.org/reading/ieee/std_public/description/testtech/1149.1-1990_desc.html IEEE 1149.1-1990] or its more recent updates (2001 and 2013, respectively) may be bought from the IEEE.</ref> after years of initial use. In the same year, [[Intel]] released their first [[Central processing unit|processor]] with JTAG (the [[80486]]) which led to quicker industry adoption by all manufacturers. In 1994, a supplement that contains a description of the [[boundary scan description language]] (BSDL) was added. Further refinements regarding the use of all-zeros for EXTEST, separating the use of SAMPLE from PRELOAD and better implementation for OBSERVE_ONLY cells were made and released in 2001.<ref name="ieee1149.1-2001">{{cite web|url=http://standards.ieee.org/reading/ieee/std_public/description/testtech/1149.1-2001_desc.html|archive-url=https://archive.today/20130415013558/http://standards.ieee.org/reading/ieee/std_public/description/testtech/1149.1-2001_desc.html|url-status=dead|archive-date=15 April 2013|url-access=subscription|title=IEEE 1149.1-2001}}</ref> Since 1990, this standard has been adopted by [[electronics]] companies around the world. [[Boundary scan]] is now mostly synonymous with JTAG, but JTAG has essential uses beyond such manufacturing applications.
The 2013<ref name="ieee1149.1-2013">{{cite web|url=https://standards.ieee.org/ieee/1149.1/4484/|url-access=subscription|title=IEEE 1149.1-2013}}</ref> revision of IEEE Std. 1149.1 has introduced a vast set of optional features, associated extensions to BSDL, and a new procedural description language (PDL) based on [[Tcl]].

=== Debugging ===
Although JTAG's early applications targeted board-level testing, here the JTAG standard was designed to assist with device, board, and system testing, [[diagnosis]], and fault isolation. Today JTAG is used as the primary means of accessing sub-blocks of [[integrated circuit]]s, making it an essential mechanism for [[debugging]] [[embedded system]]s which might not have any other debug-capable communications channel.{{citation needed|reason=This statement claims that JTAG is of critical use for a certain application but doesn't provide any source that supports the statement.|date=October 2017}} On most systems, JTAG-based debugging is available from the very first instruction after CPU reset, letting it assist with development of early [[booting|boot]] software which runs before anything is set up. An [[in-circuit emulator]] (or, more correctly, a ''JTAG adapter'') uses JTAG as the transport mechanism to access on-chip [[debug]] modules inside the target [[CPU]]. Those modules let software developers debug the software of an [[embedded system]] directly at the machine instruction level when needed, or (more typically) in terms of high-level language source code.

System software debug support is for many software developers the main reason to be interested in JTAG. Multiple silicon architectures such as PowerPC, MIPS, ARM, and x86 built an entire software debug, instruction tracing, and data tracing infrastructure around the basic JTAG protocol. Frequently individual silicon vendors however only implement parts of these extensions. Some examples are ARM [[CoreSight]] and [[Nexus (standard)|Nexus]] as well as Intel's BTS (Branch Trace Storage), LBR (Last Branch Record), and IPT (Intel Processor Trace) implementations. There are a number of other such silicon vendor-specific extensions that may not be documented except under [[Non-disclosure agreement|NDA]]. The adoption of the JTAG standard helped move JTAG-centric debugging environments away from early processor-specific designs. Processors can normally be halted, single stepped, or let run freely. One can set code breakpoints, both for code in RAM (often using a special machine instruction e.g. [[INT3]]) and in ROM/flash. Data breakpoints are often available, as is bulk data download to RAM. Most designs have ''halt mode debugging'', but some allow debuggers to access registers and data buses without needing to halt the core being debugged. Some toolchains can use ARM Embedded Trace Macrocell (ETM) modules, or equivalent implementations in other architectures to trigger debugger (or tracing) activity on complex hardware events, like a [[logic analyzer]] programmed to ignore the first seven accesses to a register from one particular subroutine.

Sometimes [[FPGA]] developers also use JTAG to develop debugging tools.<ref name="fpga">[http://www.embeddeddesignindia.co.in/ART_8800568419_2800006_TA_d2d96055.HTM Select the right FPGA debug method] {{Webarchive|url=https://web.archive.org/web/20100427145744/http://www.embeddeddesignindia.co.in/ART_8800568419_2800006_TA_d2d96055.HTM |date=27 April 2010 }} presents one of the models for such tools.</ref> The same JTAG techniques used to debug software running inside a [[CPU]] can help debug other digital design blocks inside an FPGA. For example, custom JTAG instructions can be provided to allow reading registers built from arbitrary sets of signals inside the FPGA, providing visibility for behaviors that are invisible to boundary scan operations. Similarly, writing such registers could provide controllability that is not otherwise available.

=== Storing firmware ===
JTAG allows [[Programmer (hardware)|device programmer hardware]] to transfer data into internal non-volatile device memory (e.g., [[Complex programmable logic device|CPLDs]]). Some device programmers serve a double purpose for programming as well as debugging the device. In the case of FPGAs, volatile memory devices can also be programmed via the JTAG port, normally during development work. In addition, internal monitoring capabilities (temperature, voltage, and current) may be accessible via the JTAG port.

JTAG programmers are also used to write software and data into [[flash memory]]. This is usually done using the same data bus access the CPU would use, and is sometimes handled by the CPU. In other cases the memory chips themselves have JTAG interfaces. Some modern debug architectures provide internal and external bus master access without needing to halt and take over a CPU. In the worst case, it is usually possible to drive external bus signals using the boundary scan facility.

As a practical matter, when developing an embedded system, emulating the instruction store is the fastest way to implement the ''debug cycle'' (edit, compile, download, test, and debug).{{citation needed|date=June 2015}} This is because the in-circuit emulator simulating an instruction store can be updated very quickly from the development host via, say, USB. Using a serial [[UART]] port and bootloader to upload firmware to Flash makes this debug cycle quite slow and possibly expensive in terms of tools; installing firmware into Flash (or SRAM instead of Flash) via JTAG is an intermediate solution between these extremes.

=== Boundary scan testing ===
JTAG [[boundary scan]] technology provides access to a number of logic signals of a complex integrated circuit, including the device pins. The signals are represented in the boundary scan register (BSR) accessible via the TAP. This permits testing as well as controlling the states of the signals for testing and debugging. Therefore, both software and hardware (manufacturing) faults may be located and an operating device may be monitored.

When combined with built-in self-test ([[Built-in self-test|BIST]]), the JTAG scan chain enables a low overhead, embedded solution to test an IC for certain static faults (shorts, opens, and logic errors). The scan chain mechanism does not generally help diagnose or test for timing, temperature or other dynamic operational errors that may occur. [[Test case]]s are often provided in standardized formats such as [[Serial Vector Format|SVF]], or its binary sibling XSVF, and used in production tests. The ability to perform such testing on finished boards is an essential part of [[Design For Test]] in today's products, increasing the number of faults that can be found before products ship to customers.