Editing LEON (section)

==History==
The LEON project was begun by the European Space Agency (ESA) in late 1997 to study and develop a high-performance processor to be used in European space projects.<ref>{{cite conference |last1=Andersson |first1=J. |last2=Gaisler |first2=J. |last3=Weigand |first3=R. |year=2010 |title=Next Generation Multipurpose Microprocessor |conference=DAta Systems In Aerospace 2010 (DASIA2010) |url=http://microelectronics.esa.int/gr740/NGMP-DASIA10-Paper.pdf |access-date=2020-03-17}}</ref>
The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. Another objective was to be able to manufacture in a [[single-event upset]] (SEU) tolerant sensitive semiconductor process. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient (SET) errors in combinational logic.

The LEON family includes the first LEON1 VHSIC Hardware Description Language (VHDL) design that was used in the LEONExpress test chip developed in 0.25 μm technology to prove the fault-tolerance concept. The second LEON2 VHDL design was used in the processor device AT697 from Atmel (F) and various system-on-chip devices. These two LEON implementations were developed by ESA. Gaisler Research, now part of Frontgrade (previously Aeroflex and [[Cobham plc|Cobham]]), developed the third LEON3 design and has announced the availability of the fourth generation LEON, the LEON4 processor.<ref name="gaisler1">{{cite press release|publisher=Aeroflex Gaisler|url=https://www.gaisler.com/index.php/newsevents/news-2010/337-27th-january-2010|title=Aeroflex Gaisler announces the next generation LEON processor|date=2010-01-27}}</ref>