Editing Linear-feedback shift register (section)

== Fibonacci LFSRs ==
[[File:LFSR-F16.svg|thumb|right|351 px|A 16-bit [[Fibonacci]] LFSR. The feedback tap numbers shown correspond to a primitive polynomial in the table, so the register cycles through the maximum number of 65535 states excluding the all-zeroes state. The state shown, 0xACE1 ([[hexadecimal]]) will be followed by 0x5670.]]
[[File:Fibonacci linear feedback shift register (31 bit).webm|thumb|400x400px|A Fibonacci 31 bit linear feedback shift register with taps at positions 28 and 31 (indicated by the yellow LEDs), giving it a maximum cycle and period at this speed of approximately 8 years.]]
The bit positions that affect the next state are called the ''taps''. In the diagram the taps are [16,14,13,11]. The rightmost bit of the LFSR is called the output bit, which is always also a tap.  To obtain the next state, the tap bits are XOR-ed sequentially; then, all bits are shifted one place to the right, with the rightmost bit being discarded, and that result of XOR-ing the tap bits is fed back into the now-vacant leftmost bit. To obtain the pseudorandom output stream, read the rightmost bit after each state transition.
* A maximum-length LFSR produces an [[maximum length sequence|m-sequence]] (i.e., it cycles through all possible 2<sup>''m''</sup>&nbsp;−&nbsp;1 states within the shift register except the state where all bits are zero), unless it contains all zeros, in which case it will never change.
* As an alternative to the XOR-based feedback in an LFSR, one can also use [[XNOR]].<ref>[http://www.xilinx.com/support/documentation/application_notes/xapp210.pdf Linear Feedback Shift Registers in Virtex Devices]</ref> This function is an [[affine transformation|affine map]], not strictly a [[linear map]], but it results in an equivalent polynomial counter whose state is the complement of the state of an LFSR. A state with all ones is illegal when using an XNOR feedback, in the same way as a state with all zeroes is illegal when using XOR. This state is considered illegal because the counter would remain "locked-up" in this state. This method can be advantageous in hardware LFSRs using flip-flops that start in a zero state, as it does not start in a lockup state, meaning that the register does not need to be seeded in order to begin operation.

The sequence of numbers generated by an LFSR or its XNOR counterpart can be considered a [[binary numeral system]] just as valid as [[Gray code]] or the natural binary code.
<!-- perhaps this statement should be moved to the [[binary numeral system]] article ? -->

The arrangement of taps for feedback in an LFSR can be expressed in [[finite field arithmetic]] as a [[polynomial]] [[modular arithmetic|mod]] 2. This means that the coefficients of the polynomial must be 1s or 0s. This is called the feedback polynomial or reciprocal characteristic polynomial. For example, if the taps are at the 16th, 14th, 13th and 11th bits (as shown), the feedback polynomial is

:<math>x^{16} + x^{14} + x^{13} + x^{11} + 1.</math>

The "one" in the polynomial does not correspond to a tap – it corresponds to the input to the first bit (i.e. ''x''<sup>0</sup>, which is equivalent to 1). The powers of the terms represent the tapped bits, counting from the left. The first and last bits are always connected as an input and output tap respectively.

The LFSR is maximal-length if and only if the corresponding feedback polynomial is [[primitive polynomial (field theory)|primitive]] over the [[Finite field|Galois field]] GF(2).<ref>{{Cite book |last=Gentle |first=James E. |url=https://www.worldcat.org/oclc/51534945 |title=Random number generation and Monte Carlo methods |date=2003 |publisher=Springer |isbn=0-387-00178-6 |edition=2nd |location=New York |pages=38 |oclc=51534945}}</ref><ref>{{Cite journal |last=Tausworthe |first=Robert C. |date=April 1965 |title=Random Numbers Generated by Linear Recurrence Modulo Two |url=https://www.ams.org/journals/mcom/1965-19-090/S0025-5718-1965-0184406-1/S0025-5718-1965-0184406-1.pdf |journal=Mathematics of Computation |volume=19 |issue=90 |pages=201–209|doi=10.1090/S0025-5718-1965-0184406-1 |s2cid=120804149 }}</ref> This means that the following conditions are necessary (but not sufficient):
* The number of taps is [[Even and odd numbers|even]].
* The set of taps is [[coprime integers#Coprimality in sets|setwise co-prime]]; i.e., there must be no divisor other than 1 common to all taps.

Tables of primitive polynomials from which maximum-length LFSRs can be constructed are given below and in the references.

There can be more than one maximum-length tap sequence for a given LFSR length. Also, once one maximum-length tap sequence has been found, another automatically follows. If the tap sequence in an ''n''-bit LFSR is {{nobr|[''n'', ''A'', ''B'', ''C'', 0]}}, where the 0 corresponds to the ''x''<sup>0</sup>&nbsp;=&nbsp;1 term, then the corresponding "mirror" sequence is {{nobr|[''n'', ''n'' − ''C'', ''n'' − ''B'', ''n'' − ''A'', 0]}}. So the tap sequence {{nobr|[32, 22, 2, 1, 0]}} has as its counterpart {{nobr|[32, 31, 30, 10, 0]}}. Both give a maximum-length sequence.

An example in [[C (programming language)|C]] is below:
<syntaxhighlight lang="c">
#include <stdint.h>
unsigned lfsr_fib(void)
{
    uint16_t start_state = 0xACE1u;  /* Any nonzero start state will work. */
    uint16_t lfsr = start_state;
    uint16_t bit;                    /* Must be 16-bit to allow bit<<15 later in the code */
    unsigned period = 0;

    do
    {   /* taps: 16 14 13 11; feedback polynomial: x^16 + x^14 + x^13 + x^11 + 1 */
        bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1u;
        lfsr = (lfsr >> 1) | (bit << 15);
        ++period;
    }
    while (lfsr != start_state);

    return period;
}
</syntaxhighlight>

If a fast [[parity function|parity]] or [[popcount]] operation is available, the feedback bit can be computed more efficiently as the [[dot product]] of the register with the characteristic polynomial:
*  <syntaxhighlight lang="c" inline>bit = parity(lfsr & 0x002Du);</syntaxhighlight>, or equivalently
*  <syntaxhighlight lang="c" inline>bit = popcnt(lfsr & 0x002Du) /* & 1u */;</syntaxhighlight>. (The <code>& 1u</code> turns the popcnt into a true parity function, but the bitshift later <code>bit << 15</code> makes higher bits irrelevant.)

If a rotation operation is available, the new state can be computed as
* <syntaxhighlight lang="c" inline>lfsr = rotateright((lfsr & ~1u) | (bit & 1u), 1);</syntaxhighlight>, or equivalently
* <syntaxhighlight lang="c" inline>lfsr = rotateright(((bit ^ lfsr) & 1u) ^ lfsr, 1);</syntaxhighlight>

This LFSR configuration is also known as '''standard''', '''many-to-one''' or '''external XOR gates'''. The alternative Galois configuration is described in the next section.

=== Example in Python ===
A sample python implementation of a similar (16 bit taps at [16,15,13,4]) Fibonacci LFSR would be
{{clear}}
<syntaxhighlight lang="python">
start_state = 1 << 15 | 1
lfsr = start_state
period = 0

while True:
    # taps: 16 15 13 4; feedback polynomial: x^16 + x^15 + x^13 + x^4 + 1
    bit = (lfsr ^ (lfsr >> 1) ^ (lfsr >> 3) ^ (lfsr >> 12)) & 1
    lfsr = (lfsr >> 1) | (bit << 15)
    period += 1
    if lfsr == start_state:
        print(period)
        break
</syntaxhighlight>

Where a register of 16 bits is used and the xor tap at the fourth, 13th, 15th and sixteenth bit establishes a maximum sequence length.