Editing MIPS architecture (section)

== History ==
{{expand section|date=February 2020}}
{{See also|MIPS Technologies#History|Stanford MIPS}}

The first version of the MIPS architecture was designed by [[MIPS Computer Systems]] for its [[R2000 (microprocessor)|R2000]] microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985.<ref>{{Cite web |title=The MIPS Processor |url=https://www.d.umn.edu/~gshute/mips/MIPS.html |access-date=2023-05-17 |website=www.d.umn.edu |archive-date=May 17, 2023 |archive-url=https://web.archive.org/web/20230517122920/https://www.d.umn.edu/~gshute/mips/MIPS.html |url-status=live }}</ref>{{failed verification|date=May 2023}} When MIPS II was introduced, ''MIPS'' was renamed ''MIPS I'' to distinguish it from the new version.<ref name=Sweetman1999/>{{rp|32}}

[[MIPS Computer Systems]]' [[R6000]] microprocessor (1989) was the first MIPS II implementation.<ref name=Sweetman1999/>{{rp|8}} Designed for servers, the R6000 was fabricated and sold by [[Bipolar Integrated Technology]], but was a commercial failure. During the mid-1990s, many new 32-bit MIPS processors for [[embedded system]]s were MIPS II implementations because the introduction of the 64-bit MIPS III architecture in 1991 left MIPS II as the newest 32-bit MIPS architecture until MIPS32 was introduced in 1999.<ref name=Sweetman1999/>{{rp|19}}

[[MIPS Computer Systems]]' [[R4000]] microprocessor (1991) was the first MIPS III implementation. It was designed for use in personal, workstation, and server computers. MIPS Computer Systems aggressively promoted the MIPS architecture and R4000, establishing the [[Advanced Computing Environment]] (ACE) consortium to advance its [[Advanced RISC Computing]] (ARC) standard, which aimed to establish MIPS as the dominant personal computing platform. ARC found little success in personal computers, but the R4000 (and the R4400 derivative) were widely used in workstation and server computers, especially by its largest user, [[Silicon Graphics]]. Other uses of the R4000 included high-end embedded systems and supercomputers. MIPS III was eventually implemented by a number of embedded microprocessors. [[Quantum Effect Design]]'s [[R4600]] (1993) and its derivatives was widely used in high-end embedded systems and low-end workstations and servers. MIPS Technologies' [[R4200]] (1994), was designed for embedded systems, laptop, and personal computers. A derivative, the R4300i, fabricated by [[NEC Electronics]], was used in the [[Nintendo 64]] game console. The Nintendo 64, along with the [[PlayStation (console)|PlayStation]], were among the highest volume users of MIPS architecture processors in the mid-1990s.

The first MIPS IV implementation was the MIPS Technologies [[R8000]] microprocessor chipset (1994). The design of the R8000 began at Silicon Graphics, Inc. and it was only used in high-end workstations and servers for scientific and technical applications where high performance on large floating-point workloads was important. Later implementations were the MIPS Technologies [[R10000]] (1996) and the Quantum Effect Devices [[R5000]] (1996) and [[RM7000]] (1998). The R10000, fabricated and sold by NEC Electronics and Toshiba, and its derivatives were used by NEC, Pyramid Technology, Silicon Graphics, and Tandem Computers (among others) in workstations, servers, and supercomputers. The R5000 and R7000 found use in high-end embedded systems, personal computers, and low-end workstations and servers. A derivative of the R5000 from Toshiba, the R5900, was used in Sony Computer Entertainment's [[Emotion Engine]], which powered its [[PlayStation 2]] game console.

Announced on October 21, 1996, at the Microprocessor Forum 1996 alongside the [[MDMX|MIPS Digital Media Extensions]] (MDMX) extension, MIPS V was designed to improve the performance of 3D graphics transformations.<ref>{{cite press release |date=October 21, 1996 |title=Silicon Graphics Introduces Enhanced MIPS Architecture to Lead the Interactive Digital Revolution |url=http://www.sgi.com/Headlines/1996/October/enhanced_mips.html |url-status=dead |archive-url=https://web.archive.org/web/19970606011448/http://www.sgi.com/Headlines/1996/October/enhanced_mips.html |archive-date=June 6, 1997 |publisher=[[Silicon Graphics, Inc.]]}}</ref> In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from Silicon Graphics. MIPS V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications.<ref name="MPR:1996-11-18">{{cite journal|last=Gwennap|first=Linley|date=November 18, 1996|url=http://studies.ac.upc.edu/ETSETB/SEGPAR/microprocessors/mdmx%20(mpr).pdf|title=Digital, MIPS Add Multimedia Extensions|journal=[[Microprocessor Report]]|volume=10|issue=15|pages=24–28|url-status=live|archive-url=https://web.archive.org/web/20110720095552/http://studies.ac.upc.edu/ETSETB/SEGPAR/microprocessors/mdmx%20(mpr).pdf|archive-date=July 20, 2011}}</ref> MIPS V implementations were never introduced. On May 12, 1997, Silicon Graphics announced the H1 ("Beast") and H2 ("Capitan") microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in the first half of 1999.<ref>{{cite press release |title=Silicon Graphics Previews New High-Performance MIPS Microprocessor Roadmap |date=May 12, 1997}}</ref> The H1 and H2 projects were later combined and eventually canceled in 1998. While there have not been any MIPS V implementations, MIPS64 Release 1 (1999) was based on MIPS V and retains all of its features as an optional Coprocessor 1 (FPU) feature called Paired-Single.

When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Through MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem,{{citation needed|date=June 2016}} and the architecture definition was changed to define a 32-bit and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999.<ref name="mips32-and-mips64">{{cite press release|url=http://www.thefreelibrary.com/MIPS+Technologies,+Inc.+Enhances+Architecture+to+Support+Growing+Need...-a054531136|title=MIPS Technologies, Inc. Enhances Architecture to Support Growing Need for IP Re-Use and Integration|date=May 3, 1999|publisher=[[Business Wire]]|access-date=February 11, 2016|archive-date=December 1, 2018|archive-url=https://web.archive.org/web/20181201180124/https://www.thefreelibrary.com/MIPS+Technologies%2c+Inc.+Enhances+Architecture+to+Support+Growing+Need...-a054531136|url-status=live}}</ref> MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V.<ref name="mips32-and-mips64"/> [[Nippon Electric Corporation|NEC]], [[Toshiba]] and [[SiByte]] (later acquired by [[Broadcom Corporation|Broadcom]]) each obtained licenses for MIPS64 as soon as it was announced. [[Philips]], [[LSI Corporation|LSI Logic]], [[Integrated Device Technology|IDT]], [[RMI Corporation|Raza Microelectronics, Inc.]], [[Cavium]], [[Loongson|Loongson Technology]] and [[Ingenic Semiconductor]] have since joined them. MIPS32/MIPS64 Release 5 was announced on December 6, 2012.<ref>{{cite press release|url=http://www.mips.com/news-events/newsroom/newsindex/index.dot?id=79069 |title=Latest Release of MIPS Architecture Includes Virtualization and SIMD Key Functionality for Enabling Next Generation of MIPS-Based Products|publisher=[[MIPS Technologies]]|date=December 6, 2012|archive-url=https://web.archive.org/web/20121213115846/http://www.mips.com/news-events/newsroom/newsindex/index.dot?id=79069|archive-date=December 13, 2012 }}</ref> According to the Product Marketing Director at MIPS, Release 4 was skipped because the number four is perceived as [[Tetraphobia|unlucky]] in many Asian cultures.<ref>{{cite magazine|url=http://www.eetasia.com/ART_8800679179_480100_NT_439c939b.HTM|title=MIPS skips Release 4 amid bidding war|date=December 10, 2012|magazine=[[EE Times]]|url-status=dead|archive-url=https://archive.today/20140417002825/http://www.eetasia.com/ART_8800679179_480100_NT_439c939b.HTM|archive-date=April 17, 2014}}</ref>

{{anchor|Open}}In December 2018, Wave Computing, the new owner of the MIPS architecture, announced that MIPS ISA would be open-sourced in a program dubbed the MIPS Open initiative.<ref>{{cite web|url=https://wavecomp.ai/wave-computing-extends-ai-lead-by-targeting-edge-of-cloud-through-acquisition-of-mips|title=Wave Computing Extends AI Lead by Targeting Edge of Cloud Through Acquisition of MIPS|date=June 15, 2018|access-date=December 19, 2018|archive-date=November 25, 2020|archive-url=https://web.archive.org/web/20201125030711/https://wavecomp.ai/wave-computing-extends-ai-lead-by-targeting-edge-of-cloud-through-acquisition-of-mips/|url-status=live}}</ref> The program was intended to open up access to the most recent versions of both the 32-bit and 64-bit designs making them available without any licensing or royalty fees as well as granting participants licenses to existing MIPS patents.<ref>{{cite web|url=https://wavecomp.ai/wave-computing-launches-the-mips-open-initiative|title=Wave Computing® Launches the MIPS Open Initiative To Accelerate Innovation for the Renowned MIPS® Architecture|date=December 17, 2018|access-date=December 19, 2018|archive-date=July 28, 2021|archive-url=https://web.archive.org/web/20210728072903/https://wavecomp.ai/wave-computing-launches-the-mips-open-initiative/|url-status=live}}</ref><ref>{{cite web |title=MIPS Processor ISA To Be Open-Sourced In 2019 - Phoronix |url=https://www.phoronix.com/scan.php?page=news_item&px=MIPS-Open-Source-2019 |access-date=December 18, 2018 |archive-date=March 6, 2021 |archive-url=https://web.archive.org/web/20210306084647/https://www.phoronix.com/scan.php?page=news_item&px=MIPS-Open-Source-2019 |url-status=live }}</ref><ref>{{Cite web |url=https://www.eetimes.com/mips-goes-open-source/ |title=MIPS Goes Open Source |last=Yoshida |first=Junko |date=December 17, 2018 |website=EE Times |access-date=July 18, 2022 |archive-date=July 5, 2022 |archive-url=https://web.archive.org/web/20220705124608/https://www.eetimes.com/mips-goes-open-source/ |url-status=live }}</ref>

In March 2019, one version of the architecture was made available under a royalty-free license,<ref>{{cite web|url=https://www.eetimes.com/mips-r6-architecture-now-available-for-open-use/|title=MIPS R6 Architecture Now Available for Open Use|date=March 28, 2019|access-date=December 16, 2019|archive-date=August 4, 2020|archive-url=https://web.archive.org/web/20200804035746/https://www.eetimes.com/mips-r6-architecture-now-available-for-open-use/|url-status=live}}</ref> but later that year the program was shut down again.<ref>{{cite web|url=https://www.hackster.io/news/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0|title=Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning|date=November 15, 2019|access-date=December 16, 2019|archive-date=March 7, 2021|archive-url=https://web.archive.org/web/20210307041333/https://www.hackster.io/news/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0|url-status=live}}</ref>

In March 2021, Wave Computing announced that the development of the MIPS architecture has ceased. The company has joined the RISC-V foundation and future processor designs will be based on the RISC-V architecture.<ref name="mips-becomes-risc-v" /><ref>{{cite press release|url=https://www.prnewswire.com/news-releases/wave-computing-and-mips-emerge-from-chapter-11-bankruptcy-301237051.html|title=Wave Computing and MIPS emerge from chapter 11 bankruptcy|date=March 1, 2021|access-date=March 11, 2021|archive-url=https://web.archive.org/web/20210513151210/https://www.prnewswire.com/news-releases/wave-computing-and-mips-emerge-from-chapter-11-bankruptcy-301237051.html|archive-date=May 13, 2021|url-status=live}}</ref> In spite of this, some licensees such as [[Loongson]] continue with new extension of MIPS-compatible ISAs on their own.<ref>{{cite news |last1=Shilov |first1=Anton |title=Loongson Rips MIPS: Uses Old Code for New CPUs |url=https://www.tomshardware.com/uk/news/loongson-continues-to-use-mips-code-for-loongarch-cpus |access-date=1 December 2021 |work=Tom's Hardware |date=25 August 2021 |language=en |archive-date=January 25, 2022 |archive-url=https://web.archive.org/web/20220125121447/https://www.tomshardware.com/uk/news/loongson-continues-to-use-mips-code-for-loongarch-cpus |url-status=live }}</ref>

In January 2024, Loongson won a case over rights to use MIPS architecture.<ref>{{Cite web |last=Connatser |first=Matthew |date=2024-01-19 |title=Chinese chipmaker Loongson wins case over rights to MIPS architecture - company's new CPU architecture heavily resembles existing MIPS |url=https://www.tomshardware.com/pc-components/cpus/chinese-chipmaker-loongson-wins-case-over-rights-to-mips-architecture-companys-new-cpu-architecture-heavily-resembles-existing-mips |url-status=live |archive-url=https://web.archive.org/web/20240119211100/https://www.tomshardware.com/pc-components/cpus/chinese-chipmaker-loongson-wins-case-over-rights-to-mips-architecture-companys-new-cpu-architecture-heavily-resembles-existing-mips |archive-date=2024-01-19 |access-date=2024-01-19 |website=[[Tom's Hardware]] |language=en}}</ref>