Editing Magnetic-core memory (section)

==History==

===Developers===
[[File:Project Whirlwind - core memory, circa 1951 - detail 1.JPG|thumb|[[Project Whirlwind]] core memory]]

The basic concept of using the square [[Magnetic hysteresis|hysteresis]] loop of certain magnetic materials as a storage or switching device was known from the earliest days of computer development. Much of this knowledge had developed due to an understanding of [[transformer]]s, which allowed amplification and switch-like performance when built using certain materials. The stable switching behavior was well known in the [[electrical engineering]] field, and its application in computer systems was immediate. For example, [[J. Presper Eckert]] and [[Jeffrey Chuan Chu]] had done some development work on the concept in 1945 at the [[Moore School]] during the [[ENIAC]] efforts.<ref>{{cite journal |title=A Survey of Digital Computer Memory Systems |first=J. Presper |last=Eckert |journal=Proceedings of the IRE |volume=41 |issue=10 |pages=1393–1406 |doi=10.1109/JRPROC.1953.274316 |issn=0096-8390 |publisher=IEEE |location=US |date=October 1953|s2cid=8564797 }}</ref>

Robotics pioneer [[George Devol]] filed a patent<ref>{{cite patent |number=2590091 |country=US |invent1=George C. Devol |invent2=Erik B. Hansell |title=Magnetic storage and sensing device |pubdate=10 April 1956}}</ref> for the first static (non-moving) magnetic memory on 3 April 1946. Devol's magnetic memory was further refined via 5 additional patents<ref>{{cite patent |number=2741757 |country=US |invent1=George C. Devol |invent2=Erik B. Hansell |title=Magnetic storage and sensing device |pubdate=10 April 1956}}</ref><ref>{{cite patent |number=2926844 |country=US |invent1=George C. Devol |title=Sensing device for magnetic record |pubdate=1 March 1960}}</ref><ref>{{cite patent |number=3035253 |country=US |invent1=George C. Devol |title=Magnetic storage devices |pubdate=15 May 1962}}</ref><ref>{{cite patent |number=3016465 |country=US |invent1=George C. Devol |invent2=Erik B. Hansel |title=Coincidence detectors |pubdate=9 Jan 1962}}</ref><ref>{{cite patent |number=3246219 |country=US |invent1=George C. Devol |invent2=Maurice J. Dunne |title=Ferroresonant devices |pubdate=12 April 1966}}</ref> and ultimately used in the first [[industrial robot]].  Frederick Viehe applied for various patents on the use of [[transformer]]s for building digital logic circuits in place of [[relay logic]] beginning in 1947. A fully developed core system was patented in 1947, and later purchased by [[IBM]] in 1956.<ref name=reilly1>{{cite book |title=Milestones in computer science and information technology |first=Edwin D. |last=Reilly |publisher=Greenwood Press |location=Westport, CT |year=2003 |page=[https://archive.org/details/milestonesincomp0000reil/page/164 164] |isbn=1-57356-521-0 |url=https://archive.org/details/milestonesincomp0000reil/page/164 }}</ref> This development was little-known, however, and the mainstream development of core is normally associated with three independent teams.

Substantial work in the field was carried out by the [[Shanghai]]-born [[United States|American]] [[physicist]]s [[An Wang]] and [[Way-Dong Woo]], who created the ''pulse transfer controlling device'' in 1949.<ref>{{cite journal |url=https://books.google.com/books?id=5FpRAAAAYAAJ&q=an+wang+early+work+core+memory |title=Wang Interview, An Wang's Early Work in Core Memories |journal=Datamation |publisher=Technical Publishing Company |location=US |date=March 1976 |pages=161–163}}</ref> The patent described a type of memory that would today be known as a [[Delay-line memory|delay-line]] or [[shift-register]] system. Each bit was stored using a pair of transformers, one that held the value and a second used for control. A [[signal generator]] produced a series of pulses which were sent into the control transformers at half the energy needed to flip the polarity. The pulses were timed so the field in the transformers had not faded away before the next pulse arrived. If the storage transformer's field matched the field created by the pulse, then the total energy would cause a pulse to be injected into the next transformer pair. Those that did not contain a value simply faded out. Stored values were thus moved bit by bit down the chain with every pulse. Values were read out at the end, and fed back into the start of the chain to keep the values continually cycling through the system.<ref>{{cite patent |inventor-first=An |inventor-last=Wang |title=Pulse Transfer Controlling Device |gdate=17 May 2020 |country=US |number=2708722 |url=https://patents.google.com/patent/US2708722A/en?oq=US2708722+}}</ref> Such systems have the disadvantage of not being random-access, to read any particular value one has to wait for it to cycle through the chain. Wang and Woo were working at [[Harvard University]]'s Computation Laboratory at the time, and the university was not interested in promoting inventions created in their labs. Wang was able to patent the system on his own.

The MIT [[Project Whirlwind]] computer required a fast memory system for [[Real-time computing|real-time]] aircraft tracking. At first, an array of [[Williams tube]]s&mdash;a storage system based on [[cathode-ray tube]]s&mdash;was used, but proved  temperamental and unreliable. Several researchers in the late 1940s conceived the idea of using magnetic cores for computer memory, but MIT computer engineer [[Jay Forrester]] received the principal patent for his invention of the coincident-current core memory that enabled the 3D storage of information.<ref>{{cite journal |first=Jay W. |last=Forrester |title=Digital Information Storage In Three Dimensions Using Magnetic Cores |journal=Journal of Applied Physics |issue=1 |year=1951|volume=22 |pages=44–48 |doi=10.1063/1.1699817 |bibcode=1951JAP....22...44F }}</ref><ref>{{cite patent |inventor-first=Jay W. |inventor-last=Forrester |title=Multicoordinate digital information storage device |country=US |number=2736880 |gdate=28 February 1956}}</ref> William Papian of Project Whirlwind cited one of these efforts, Harvard's "Static Magnetic Delay Line", in an internal memo. The first core memory of {{nobr|32 × 32 × 16 bits}} was installed on Whirlwind in the summer of 1953. Papian stated: "Magnetic-Core Storage has two big advantages: (1) greater reliability with a consequent reduction in maintenance time devoted to storage; (2) shorter access time (core access time is 9 microseconds: tube access time is approximately 25 microseconds) thus increasing the speed of computer operation."<ref>{{cite journal |url=http://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/TCMR-1983_Winter_A_Companion_to_the_Computer_Pioneer_Timeline.pdf |title=Whirlwind |page=13 |journal=The Computer Museum Report |publisher=The Computer Museum |location=Massachusetts |date=Winter 1983 |via=Microsoft}}</ref>

In April 2011, Forrester recalled, "the Wang use of cores did not have any influence on my development of random-access memory. The Wang memory was expensive and complicated. As I recall, which may not be entirely correct, it used two cores per binary bit and was essentially a delay line that moved a bit forward. To the extent that I may have focused on it, the approach was not suitable for our purposes." He describes the invention and associated events, in 1975.<ref>{{cite journal |title=Conversation: Jay W. Forrester |first=Christopher |last=Evans |journal=Annals of the History of Computing |volume= 5 |number=3 |date=July 1983 |pages=297–301 |doi=10.1109/mahc.1983.10081|s2cid=25146240 }}</ref> Forrester has since observed, "It took us about seven years to convince the industry that random-access magnetic-core memory was the solution to a missing link in computer technology.  Then we spent the following seven years in the patent courts convincing them that they had not all thought of it first."<ref>{{cite web |url=http://sloanreview.mit.edu/feature/jay-forrester-shock-to-the-system/ |title=Jay Forrester's Shock to the System |first=Art |last=Kleiner |work=The MIT Sloan Review |location=US |date=4 February 2009 |access-date=1 April 2018}}</ref>

A third developer involved in the early development of core was [[Jan A. Rajchman]] at [[RCA]]. A prolific inventor, Rajchman designed a unique core system using ferrite bands wrapped around thin metal tubes,<ref>Jan A. Rajchman, Magnetic System, {{US patent|2792563}}, granted 14 May 1957.</ref> building his first examples using a converted [[aspirin]] press in 1949.<ref name=reilly1/> Rajchman later developed versions of the Williams tube and led development of the [[Selectron tube|Selectron]].<ref>{{cite journal |first=William |last=Hittinger |url=http://books.nap.edu/openbook.php?isbn=0309046890&page=229 |title=Jan A. Rajchman |journal=Memorial Tributes |publisher=National Academy of Engineering |location=US |volume=5 |page=229 |year=1992}}</ref>

Two key inventions led to the development of magnetic core memory in 1951. The first, An Wang's, was the write-after-read cycle, which solved the problem of how to use a storage medium in which the act of reading erased the data read, enabling the construction of a serial, one-dimensional [[shift register]] (of 50 bits), using two cores to store a bit. A Wang core shift register is in the Revolution exhibit at the [[Computer History Museum]]. The second, Forrester's, was the coincident-current system, which enabled a small number of wires to control a large number of cores enabling 3D memory arrays of several million bits. The first use of magnetic core was in the Whirlwind computer,<ref>{{cite book |title=Computer Architecture and Organization |last=Hayes |first=John P. |isbn=0-07-027363-4 |year=1978 |page=21 |publisher=McGraw-Hill International Book Company }}</ref> and Project Whirlwind's "most famous contribution was the random-access, magnetic core storage feature."<ref name=PWbook>{{cite book |last1=Redmond |first1=Kent C. |last2=Smith |first2=Thomas M. |title=Project Whirlwind - The History of a Pioneer Computer |page=215 |date=1980 |publisher=Digital Press |location=Bedford, Mass. |isbn=0932376096}}</ref> Commercialization followed quickly.  Magnetic core was used in peripherals of the [[ENIAC]] in 1953,<ref>{{cite book |chapter-url=https://dl.acm.org/doi/abs/10.1145/609784.609813 |doi=10.1145/609784.609813 |isbn=9781450373623 |chapter=A static magnetic memory system for the ENIAC |date=2 May 1952 |pages=213–222|title=Proceedings of the 1952 ACM national meeting (Pittsburgh) on - ACM '52 |last1=Auerbach |first1=Isaac L. |s2cid=17518946 }}</ref> the [[IBM 702]]<ref>{{cite book |first1=Emerson W. |last1=Pugh |first2=Lyle R. |last2=Johnson |first3=John H. |last3=Palmer |title=IBM's 360 and Early 370 Systems |date=1991 |publisher=MIT Press |isbn=978-0-262-51720-1 |page=32}}</ref> delivered in July 1955, and later in the 702 itself.  The [[IBM 704]] (1954) and the [[Ferranti Mercury]] (1957) used magnetic-core memory.

It was during the early 1950s that [[Seeburg Corporation]] developed one of the first commercial applications of coincident-current core memory storage in the "Tormat" memory of its new range of [[jukebox]]es, starting with the V200 developed in 1953 and released in 1955.<ref>Clarence Schultz and George Boesen, Selectors for Automatic Phonographs, {{US patent|2923553A}}, granted Feb. 2, 1960.</ref> Numerous uses in computing, telephony and industrial [[process control]] followed.

===Patent disputes===
Wang's patent was not granted until 1955, and by that time magnetic-core memory was already in use. This started a long series of lawsuits, which eventually ended when [[IBM]] bought the patent outright from Wang for {{USD|500,000}}.<ref>{{cite web|url=http://www.computerhistory.org/tdih/March/4/ |title=An Wang Sells Core Memory Patent to IBM |access-date=12 April 2010 |publisher=Computer History Museum |location=US}}</ref> Wang used the funds to greatly expand [[Wang Laboratories]], which he had co-founded with Dr. Ge-Yao Chu, a schoolmate from China.

MIT wanted to charge IBM $0.02 per bit royalty on core memory.  In 1964, after years of legal wrangling, IBM paid MIT $13 million for rights to Forrester's patent—the largest patent settlement to that date.<ref>{{cite web |url=http://www.computerhistory.org/revolution/memory-storage/8/253 |title=Magnetic Core Memory |work=CHM Revolution |publisher=Computer History Museum |access-date=1 April 2018}}</ref><ref>{{harvnb|Pugh|Johnson|Palmer|1991|p=[https://archive.org/details/ibms360early370s0000pugh/page/182 182] }}</ref>

===Production economics===
In 1953, tested but not-yet-strung cores cost {{USD|0.33}} each.  As manufacturing volume increased, by 1970 IBM was producing 20 billion cores per year, and the price per core fell to {{USD|0.0003}}.  Core sizes shrank over the same period from around {{convert|0.1|inch|mm|abbr=out}} diameter in the 1950s to {{convert|0.013|inch|mm}} in 1966.<ref>{{harvnb|Pugh|Johnson|Palmer|1991|pp=[https://archive.org/details/ibms360early370s0000pugh/page/204 204–6]}}</ref>  The power required to flip the magnetization of one core is proportional to the volume, so this represents a drop in power consumption by a factor of 125.

The cost of complete core memory systems was dominated by the cost of stringing the wires through the cores.  Forrester's coincident-current system required one of the wires to be run at 45 degrees to the cores, which proved difficult to wire by machine, so that core arrays had to be assembled under microscopes by workers with fine motor control.

In 1956, a group at IBM filed for a patent on a machine to automatically thread the first few wires through each core.  This machine held the full plane of cores in a "nest" and then pushed an array of hollow needles through the cores to guide the wires.<ref>Walter P. Shaw and Roderick W. Link, Method and Apparatus for Threading Perforated Articles, {{US patent|2958126}}, granted Nov. 1, 1960.</ref>  Use of this machine reduced the time taken to thread the straight X and Y select lines from 25 hours to 12 minutes on a 128 by 128 core array.<ref>{{cite book |title=IBM's Early Computers |first1=Charles J. |last1=Bashe |first2=Lyle R. |last2=Johnson |first3=John H. |last3=Palmer |publisher=MIT Press |location=Cambridge, MA |year=1986 |pages=268 |isbn=0-262-52393-0}}</ref>

Smaller cores made the use of hollow needles impractical, but there were numerous advances in semi-automatic core threading.  Support nests with guide channels were developed. Cores were permanently bonded to a backing sheet "patch" that supported them during manufacture and later use. Threading needles were [[Butt welding|butt welded]] to the wires, the needle and wire diameters were the same, and efforts were made to eliminate the use of needles.<ref>Robert L. Judge, Wire Threading Method and Apparatus, {{US patent|3314131}}, granted Apr. 18, 1967.</ref><ref>Ronald A. Beck and Dennis L. Breu, Core Patch Stringing Method, {{US patent|3872581}}, granted Mar. 25, 1975.</ref>

The most important change, from the point of view of automation, was the combination of the sense and inhibit wires, eliminating the need for a circuitous diagonal sense wire.  With small changes in layout, this also allowed much tighter packing of the cores in each patch.<ref name=US3329940>Creighton D. Barnes, et al., Magnetic core storage device having a single winding for both the sensing and inhibit function, {{US patent|3329940}}, granted 4 July 1967.</ref><ref name=US3711839>Victor L. Sell and Syed Alvi, High Density Core Memory Matrix, {{US patent|3711839}}, granted Jan. 16, 1973.</ref>

By the early 1960s, the cost of core fell to the point that it became nearly universal as [[main memory]], replacing both inexpensive low-performance [[drum memory]] and costly high-performance systems using [[vacuum tube]]s, and later discrete [[transistor]]s as memory. The cost of core memory declined sharply over the lifetime of the technology: costs began at roughly {{USD|1.00}} per bit and dropped to roughly {{USD|0.01}} per bit.

Core memory was made [[obsolete]] by [[semiconductor memory|semiconductor]] [[integrated circuit]] memories in the 1970s, though remained in use for mission-critical and high-reliability applications in the [[IBM System/4 Pi#AP-101|IBM System/4 Pi AP-101]] (used in the [[Space Shuttle]] until an upgrade in early 1990s, and the [[B-52]] and [[B-1B]] bombers).<ref>{{Cite web |title=Project History: Magnetic Core Memory |url=https://web.mit.edu/6.933/www/core.html |access-date=2023-07-14 |website=web.mit.edu |archive-url=https://web.archive.org/web/20230714195033/https://web.mit.edu/6.933/www/core.html |archive-date=2023-07-14 |url-status=dead}}</ref><ref>{{Citation |author=Norman, P. Glenn |title=The new AP101S General-Purpose Computer (GPC) for the Space Shuttle |journal=IEEE Proceedings |volume=75 |issue=3 |pages=308–319 |year=1987 |bibcode=1987IEEEP..75..308N |doi=10.1109/PROC.1987.13738 |s2cid=19179436}}</ref><ref>{{cite book |last1=Stormont |first1=D.P. |last2=Welgan |first2=R. |title=Proceedings of National Aerospace and Electronics Conference (NAECON'94) |chapter=Risk management for the B-1B computer upgrade |date=23–27 May 1994 |chapter-url=https://zenodo.org/record/1232223 |volume=2 |pages=1143–1149 |doi=10.1109/NAECON.1994.332913 |isbn=0-7803-1893-5 |s2cid=109575632}}<!--|access-date=23 October 2013--></ref>

An example of the scale, economics, and technology of core memory in the 1960s was the 256K 36-bit word (1.2&nbsp;[[MiB]]<ref>Internally, the Moby Memory had 40 bits per word, but they were not exposed to the PDP-10 processor.</ref>) core memory unit installed on the [[PDP-6]] at the [[MIT Computer Science and Artificial Intelligence Laboratory|MIT Artificial Intelligence Laboratory]] by 1967.<ref>{{cite report |url=https://apps.dtic.mil/dtic/tr/fulltext/u2/681342.pdf |archive-url=https://web.archive.org/web/20210508105745/https://apps.dtic.mil/dtic/tr/fulltext/u2/681342.pdf |url-status=dead |archive-date=8 May 2021 |publisher=Massachusetts Institute of Technology |title=Project MAC. Progress Report IV. July 1966-July 1967 |page=18 |id=681342 |access-date=2020-12-07}}</ref> This was considered "unimaginably huge" at the time, and nicknamed the "Moby Memory".<ref>[[Eric S. Raymond]], [[Guy L. Steele]], ''The New Hacker's Dictionary'', 3rd edition, 1996, {{isbn|0262680920}}, based on the [[Jargon File]], ''s.v.'' 'moby', p. 307</ref> It cost $380,000 ($0.04/bit) and its width, height and depth was {{cvt|69|x|50|x|25|in|cm|0|order=flip}} with its supporting circuitry (189 kilobits/cubic foot = 6.7 kilobits/litre). Its cycle time was 2.75&nbsp;μs.<ref>{{cite book |url=https://www.computerhistory.org/collections/catalog/102731715 |title=FABRI-TEK Mass Core 'Moby' Memory |website=Computer History Museum |date=4 August 1967 |location=US |id=102731715 |access-date=2020-12-07}}</ref><ref>{{cite web |url=http://ljkrakauer.com/LJK/60s/moby.htm |title=Moby Memory  |first=Lawrence J. |last=Krakauer |access-date=2020-12-07}}</ref><ref>Steven Levy, ''Hackers: Heroes of the Computer Revolution'', 2010 (25th anniversary edition), {{isbn|1449393748}}, p. 98</ref>

In 1980, the price of a 16&nbsp;kW ([[kiloword]], equivalent to 32&nbsp;kB) core memory board that fitted into a DEC Q-bus computer was around {{USD|3,000}}. At that time, core array and supporting electronics could fit on a single printed circuit board about {{cvt|25|x|20|cm|in|0}} in size, the core array was mounted a few mm above the PCB and was protected with a metal or plastic plate.{{cn|date=July 2024}}