Editing Montecito (processor) (section)

==Architectural features and attributes==
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* '''Two [[Multi-core processor|cores]]''' per [[die (integrated circuit)|die]]
* '''2-way''' coarse-grained '''[[Multithreading (computer architecture)|multithreading]]''' per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. This is also known as switch-on-event multithreading, or SoEMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high [[latency (engineering)|latency]] event, like an L3 [[CPU cache|cache miss]] which would otherwise stall execution. By this technique, multi-threaded workloads, including [[database]]-like workloads, should improve by 15-35%.{{Citation needed|date=February 2008}}
* a total of '''4 threads per die'''
* separate '''16 [[kilobyte|KB]] Instruction L1 and 16 KB Data L1 cache per core'''
* separate '''1 [[megabyte|MB]] Instruction L2 and 256 KB Data L2 cache per core''', improved [[memory hierarchy|hierarchy]]
* '''12 MB L3''' cache per core, '''24 MB L3''' per die
* '''1.72 billion [[transistor]]s''' per die, which is added up from:
** core [[digital circuit|logic]] — 57M, or 28.5M per core
** core caches — 106.5M
** 24 MB L3 cache — 1550M
** [[computer bus|bus]] logic & [[input/output|I/O]] — 6.7M
* Die size is 27.72&nbsp;mm × 21.5&nbsp;mm, or 596&nbsp;mm<sup>2</sup>
* '''[[90 nanometer]] design'''
* '''Lower [[electric power|power]] consumption and [[heat|thermal]] dissipation''' than earlier flagship Itaniums, despite the high transistor count; '''75-104&nbsp;[[watt|W]]'''. This is mainly achieved by applying different types of transistors. By default, slower and low-[[leakage (semiconductors)|leakage]] transistors were used, while high-speed, thus high-leakage ones where it was necessary.
* Advanced '''compensation for errors''' in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology.
* '''Virtualization''' technology allowing multiple OS instances per chip. This was known as Silvervale technology during development, and is now called Intel Virtualization Technology.
* Improved, '''higher [[bandwidth (computing)|bandwidth]]''' [[front side bus]] (FSB), with three times the capacity of the existing bus design. It is meant to be at system level (per node, with 4 dies). System [[throughput]] per node should be at least 21 [[gigabyte|GB]]/[[second|s]], which suggest dual 333.333&nbsp;MHz ([[double data rate|double pumped]], resulting 2×667 effective MHz) front side bus. However, it is up to system integrators how they organize their bus topology.
* All Montecito processors support 533&nbsp;MHz / 400&nbsp;MHz FSB speed.
* Also available with [[legacy system|legacy]] FSB for [[upgrade|upgrading]] existing system designs.
* Eliminates the hardware-based [[x86 architecture|x86]] instruction emulation circuitry, in favor of the more efficient software-based [[IA-32 Execution Layer]].[https://archive.today/20130119155009/http://news.com.com/2100-1006_3-6028817.html]

On October 25, 2005, Intel announced that the first dual-core Itanium processor would be delayed until "the middle of next year." [http://www.pcworld.com/news/article/0,aid,123190,00.asp] {{Webarchive|url=https://web.archive.org/web/20080516112152/http://www.pcworld.com/news/article/0,aid,123190,00.asp |date=2008-05-16 }} Montecito was launched on July 18, 2006. Due to unspecified issues, Intel's [[Foxton Technology|Foxton power management technology]] was disabled in the first release of Montecito, and the front-side bus frequency was reduced to 267&nbsp;MHz (533.333&nbsp;MHz effective) instead of the 333&nbsp;MHz speed originally scheduled for the design [3].

At the time of launch, the following models and pricing were available: 
 
* Itanium 2 9050 1.60&nbsp;[[gigahertz|GHz]] / 24&nbsp;MB L3 &mdash; $3,692
* Itanium 2 9040 1.60&nbsp;GHz / 16&nbsp;MB L3 &mdash; $1,980
* Itanium 2 9030 1.60&nbsp;GHz / 8&nbsp;MB L3 &mdash; $1,552
* Itanium 2 9020 1.42&nbsp;GHz / 12&nbsp;MB L3 &mdash; $910
* Itanium 2 9015 1.40&nbsp;GHz / 12&nbsp;MB L3 &mdash; $749
* Itanium 2 9010 1.60&nbsp;GHz / 6&nbsp;MB L3 / single core &mdash; $696

There are no plans for additional Montecito processors; the successor, Montvale was released in late 2007.