Editing NMOS logic (section)

==Overview==
MOS stands for ''metal-oxide-semiconductor'', reflecting the way MOS-transistors were originally constructed, predominantly before the 1970s, with gates of metal, typically aluminium. Since around 1970, however, most MOS circuits have used [[self-aligned gate]]s made of [[polycrystalline silicon]], a technology first developed by [[Federico Faggin]] at [[Fairchild Semiconductor]]. These [[silicon gate]]s are still used in most types of MOSFET based [[integrated circuit]]s, although metal gates ([[Aluminium|Al]] or [[Copper|Cu]]) started to reappear in the early 2000s for certain types of high speed circuits, such as high performance microprocessors.

The MOSFETs are n-type [[enhancement mode]] transistors, arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage (typically the ground). A [[pull up resistor|pull up]] (i.e. a "load" that can be thought of as a resistor, see below) is placed between the positive supply voltage and each logic gate output. Any [[logic gate]], including the [[logic gate#inverter|logical inverter]], can then be implemented by designing a network of parallel and/or series circuits, such that if the desired output for a certain combination of [[boolean data type|boolean]] input values is [[boolean logic|zero]] (or [[boolean logic|false]]), the PDN will be active, meaning that at least one transistor is allowing a current path between the negative supply and the output. This causes a voltage drop over the load, and thus a low voltage at the output, representing the ''zero.''
[[Image:NMOS NOR WITH RESISTIVE LOAD.PNG|200px|thumb|The R-pulled circuit acts like a NOR gate that sinks OUT to the GND.]]

As an example, here is a [[Logical NOR|NOR]] gate implemented in schematic NMOS.  If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False).  When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which occurs only when both A and B are low, thus satisfying the truth table of a NOR gate:

{| class="wikitable"N-type metal–oxide–semiconductor logic uses n-type field-effect transistors (MOSFETs) to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation. 
! A !! B !! A NOR B
|- align=center
| 0 || 0 || 1
|- align=center
| 0 || 1 || 0
|- align=center
| 1 || 0 || 0
|- align=center
| 1 || 1 || 0
|}

A MOSFET can  be made to operate as a resistor, so the whole circuit can be made with n-channel MOSFETs only. NMOS circuits are slow to transition from low to high.  When transitioning from high to low, the transistors provide low resistance, and the capacitive charge at the output drains away very quickly (similar to discharging a capacitor through a very low resistor). But the resistance between the output and the positive supply rail is much greater, so the low to high transition takes longer (similar to charging a capacitor through a high value resistor). Using a resistor of lower value will speed up the process but also increases static power dissipation. However, a better (and the most common) way to make the gates faster is to use [[Depletion-load NMOS logic|depletion-mode]] transistors instead of [[MOSFET|enhancement-mode]] transistors as loads. This is called [[depletion-load NMOS logic]].