Editing NOP (code) (section)

== Machine language instructions ==
Some computer [[instruction set]]s include an instruction whose purpose is to not change the state of any of the programmer-accessible [[Processor register|registers]], [[Process states|status flags]], or [[main memory|memory]]. It often takes a well-defined number of [[clock cycles]] to execute. In other instruction sets, there is no explicit NOP instruction, but the assembly language mnemonic NOP represents an instruction which acts as a NOP; e.g., on the [[SPARC]], <code>sethi 0, %g0</code>.

A NOP must not access memory, as that could cause a [[memory fault]] or [[page fault]]. 

A NOP is most commonly used for timing purposes, to force [[Data structure alignment|memory alignment]], to prevent [[hazard (computer architecture)|hazard]]s, to occupy a [[branch delay slot]], to render void an existing instruction such as a jump, as a target of an [[execute instruction]], or as a place-holder to be replaced by active instructions later on in program development (or to replace removed instructions when reorganizing would be problematic or time-consuming). In some cases, a NOP can have minor side effects; for example, on the [[Motorola 68000]] series of processors, the NOP opcode causes a synchronization of the [[pipeline (computing)|pipeline]].<ref name=m68ref>{{cite web|url=https://www.nxp.com/docs/en/reference-manual/M68000PRM.pdf|title=Motorola 68000 Programmer's Reference Manual}}</ref>

Listed below are the NOP instruction for some CPU architectures:

{{sticky header}}
{| class="wikitable  sticky-header" border="1"
|-
! CPU architecture
! Instruction [[mnemonic]]
! [[Byte]]s
! [[Opcode]]
! Notes
|-
| rowspan=2 | [[Intel]] [[x86]] [[central processing unit|CPU]] family
| <code>NOP</code>
| 1
| 0x90<ref name="x86-instruction-set-intel">{{cite web |url=https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html|title=Intel 64 and IA-32 Architectures Software Developer's Manual: Instruction Set Reference A-Z|access-date=2012-03-01}}</ref>
| 0x90 is the one-byte encoding for <code>XCHG AX,AX</code> in 16-bit code and <code>XCHG EAX,EAX</code> in 32-bit code. In long mode, <code>XCHG RAX,RAX</code> requires two bytes, as it would begin with an <code>REX.W</code> prefix, making the encoding 0x48 0x90.  However, 0x90 is interpreted as a <code>NOP</code> in long mode regardless of whether it is preceded by 0x48.<ref name="x86-instruction-set-intel" />
|-
| multi-byte <code>NOP</code>
| 2–9 for [[Pentium Pro]] and later Intel processors, and all AMD AMD64 processors
| 0x66 0x90<br />
0x0F 0x1F 0x00<br />

0x0F 0x1F 0x40 0x00<br />

0x0F 0x1F 0x44 0x00 0x00<br />

0x66 0x0F 0x1F 0x44 0x00 0x00<br />

0x0F 0x1F 0x80 0x00 0x00 0x00 0x00<br />

0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00<br />

0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00<ref name="x86-instruction-set-intel" />
| 0x66 is the operand-size override prefix.

0x0F 0x1F is a two-byte NOP opcode that takes a [[ModR/M]] operand upon which no memory is accessed and no registers are written. Operands added to this are:

0x00 is <code>[EAX]</code>

0x40 0x00 is <code>[EAX + 00H]</code>

0x44 0x00 0x00 is <code>[EAX + EAX*1 + 00H]</code>

0x80 0x00 0x00 0x00 0x00 is <code>[EAX + 00000000H]</code>

0x84 0x00 0x00 0x00 0x00 0x00 is <code>[EAX + EAX*1 + 00000000H]</code><ref name="x86-instruction-set-intel" />
|-
| [[Intel 8008]]
| <code>LAA</code>
| 1
| 0xC0
| Load A from A
|-
| [[Intel]] [[8051]] / [[MCS-51]] family
| <code>NOP</code>
| 1
| 0x00
|
|-
| [[Intel 8080]], [[Intel 8085]], [[Z80]]
| <code>NOP</code>
| 1
| 0x00
|
|-
| rowspan=2 | [[Intel i860]]
| <code>NOP</code>
| 4
| 0xA0000000
| Core no-operation. Opcode for {{nowrap|<code>shl r0,r0,r0</code>,}} an instruction to left-shift the all-0s register by itself.<ref name="i860">Intel, [https://bitsavers.org/components/intel/i860/240329-002_i860_64-Bit_Microprocessor_Programmers_Reference_Feb89.pdf i860 64-bit Microprocessor Programmer's Reference Manual], order no. 240329-002, Feb 1989, pages 68 and 172.</ref>
|-
| <code>FNOP</code>
| 4
| 0xB0000000
| Floating-point no-operation. Opcode for {{nowrap|<code>shrd r0,r0,r0</code>}}, a shift-right-double instruction that takes the all-0s register as input and output.<ref name="i860"/>
|-
| [[Intel i960]]
| <code>MOV g0,g0</code>
| 4
| 0x5C801610
| Move global register g0 to itself. Suggested opcode for cases where a no-op is needed.<ref>Intel, [https://web.archive.org/web/20030415021156/http://intel.com:80/design/i960/manuals/27248402.pdf i960 Hx Microprocessor Developer’s Manual], order no. 272484-002, September 1998 - see appendix B on p. 487 and appendix C on pp. 495-497 for instruction encoding, and appendix E.2.7.8 on p. 575 for the use of {{nowrap|MOV g0,g0}} as a padding-NOP. Archived from the [http://intel.com/design/i960/manuals/27248402.pdf original] on 15 Apr 2003.</ref>
|-
| rowspan=5 | [[Intel]] [[IA-64]] ([[Itanium]])
| <code>(qp) NOP.b imm21</code>
| 41 bits
| 0x04000000000
| rowspan=5 | On IA-64, the <code>NOP</code> instruction has five forms, each of which can be executed only on a particular execution unit type.<ref>Intel, [https://www.intel.com/content/dam/doc/manual/itanium-architecture-vol-1-2-3-4-reference-set-manual.pdf Intel Itanium Architecture Software Developer’s Manual rev 2.3], May 2010. Book 3 section 2.2 on page 1092, section 4.3.4.1 on page 1218, section 4.4.11 on page 1248, section 4.5.3.2 on page 1255, section 4.6.9.2 on page 1264 and section 4.7.4 on page 1267. [https://web.archive.org/web/20111208182434/https://www.intel.com/content/dam/doc/manual/itanium-architecture-vol-1-2-3-4-reference-set-manual.pdf Archived] on 8 Dec 2011.</ref>

All five <code>NOP</code> forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s - which is common but not required).

The <code>NOP.x</code> form of the instruction additionally consumes a second 41-bit instruction slot - the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits.
|-
| <code>(qp) NOP.f imm21</code>
| rowspan=3 | 41 bits
| rowspan=3 | 0x00008000000
|-
| <code>(qp) NOP.i imm21</code>
|-
| <code>(qp) NOP.m imm21</code>
|-
| {{nowrap|<code>(qp) NOP.x imm62</code>}}
| 41+41 bits
| 0x00008000000 imm41
|-
! colspan=5 |
|-
| rowspan=4 | [[ARM architecture|ARM A32]]
| <code>NOP</code> || 4 || 0x*320F000
| Architectural ARM A32 NOP ("true" nop, with no register dependencies). Introduced with ARMv6K ([[ARM 11]]76, released in 2003), and present in all later ARM A32 processors. (The * indicates a 4-bit field that may take any value other than 0xF.)<ref name="arm_ddi_0406">ARM, [https://documentation-service.arm.com/static/5f8daeb7f86e16515cdb8c4e ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition], ARM DDI 0406C.d, 29 Mar 2018, section A8.8.120 on page 511. [https://web.archive.org/web/20230927135324/https://documentation-service.arm.com/static/5f8daeb7f86e16515cdb8c4e Archived] on 27 Sep 2023.</ref>
|-
| <code>MOV r0,r0</code>/<code>NOP</code> || 4 || 0xE1A00000
| Recommended A32 no-operation encoding for older 32-bit ARM processors that pre-date ARMv6K. Assemblers for A32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6K or later versions of the ARM architecture.<ref name="arm_dui_0041c">ARM, [https://documentation-service.arm.com/static/604f2c8aefb1a112dce66ba1 ARM Software Development Toolkit Version 2.50 Reference Guide], ARM DUI 0041C, Nov 1998, see sections 5.5.6 and 5.6.4 for NOPs in ARM/Thumb assembly. [https://web.archive.org/web/20220601052534/https://documentation-service.arm.com/static/604f2c8aefb1a112dce66ba1 Archived] on 1 Jun 2022.</ref><ref name="arm_asmref">ARM, [https://developer.arm.com/documentation/dui0489/i/Cjafcggi?lang=en ARM Compiler toolchain Assembler Reference v5.03, NOP instruction]. [https://archive.today/20250316203453/https://developer.arm.com/documentation/dui0489/i/Cjafcggi?lang=en Archived] on 16 Mar 2025.</ref>
|-
| <code>ANDEQ r0,r0,r0</code> || 4 || 0x00000000
| Bitwise-AND r0 with itself if equal. Commonly used no-op encoding due to the simplicity of its encoding.<ref name="osmith96">O. Smith, [https://groups.google.com/g/comp.sys.arm/c/KDFGkeBRTPk/m/G5CMf41k-0QJ StrongARM multiply speed], 12 Dec 1996. [https://web.archive.org/web/20250316212058/https://groups.google.com/g/comp.sys.arm/c/KDFGkeBRTPk/m/G5CMf41k-0QJ Archived] on 16 Mar 2025.</ref>
|-
| <code>MOVNV r0,r0</code> || 4 || 0xF1A00000
| Move r0 to itself never. Obsolete no-op encoding that used to be recommended for the ARM2/ARM3 processors in older [[Acorn Archimedes]] computers.<ref name="osmith96"/><ref>Acorn Computers, [https://www.4corn.co.uk/archive/docs/Acorn%20Assembler%20Release%202-opt.pdf Acorn Assembler Release 2], May 1991. MOVNV listed on page 218. [https://web.archive.org/web/20181025200615/https://www.4corn.co.uk/archive/docs/Acorn%20Assembler%20Release%202-opt.pdf Archived] on 25 Oct 2018.</ref> Makes use of the NV ("never") condition code — which has been deprecated since 1993,<ref>ARM, [https://bitsavers.org/pdf/acorn/ARM_DDI_0004D_ARM610_Data_Sheet_Aug93.pdf ARM610 32 Bit RISC Microprocessor], ARM DDI 0004D, Aug 1993, page 20</ref> with support fully removed with ARMv5.<ref>ARM, [https://kib.kiev.ua/x86docs/ARM/ARMARMv5/DDI0100D.pdf ARM Architecture Reference Manual], ARM DDI 0100D, Feb 2000, section 3.2.1 on page 69. [https://web.archive.org/web/20250316210245/https://kib.kiev.ua/x86docs/ARM/ARMARMv5/DDI0100D.pdf Archived] on 16 Feb 2025.</ref>
|-
| rowspan=3 | [[ARM architecture#Thumb-2|ARM T32]] (Thumb)
| <code>NOP</code> || 2 || 0xBF00
| rowspan=2 | Architectural ARM T32 (Thumb-2) NOPs ("true" nops, with no register dependencies). Introduced with ARMv6T2 ([[ARM 11]]56, released in 2003), and present in all later ARM T32 processors.<ref name="arm_ddi_0406"/><!-- earlier revisions of this page listed 0xB000 ADD SP,#0, however there does not appear to exist any references outside wikipedia for the claim that this has been used or recommended as a NOP -->
|-
| <code>NOP.W</code> || 4 || 0xF3AF8000
|-
| <code>MOV r8,r8</code>/<code>NOP</code> || 2 || 0x46C0
| Recommended Thumb no-operation encoding for older 32-bit Thumb processors that pre-date ARMv6T2. Assemblers for T32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6T2 or later versions of the ARM Thumb architecture.<ref name="arm_dui_0041c"/><ref name="arm_asmref"/>
|-
| [[ARM architecture#ARMv8_and_64-bit|ARM A64]] (64 bit)
| <code>NOP</code>
| 4
| 0xD503201F
| Architectural NOP.
|-
! colspan=5 |
|-
| rowspan=3 | [[DEC Alpha]]
| <code>NOP</code>
| 4
| 0x47FF041F
| Integer NOP. Opcode for <code>BIS r31,r31,r31</code>, an instruction that bitwise-ORs the always-0 register with itself.<ref name="alpha_handbook4">Compaq, [https://web.archive.org/web/20040827035155/http://ftp.digital.com:80/pub/Digital/DECinfo/semiconductor/literature/alphaahb.pdf Alpha Architecture Handbook] version 4, order no: EC–QD2KC–TE, October 1998 - see section A.4.4.1 on p.285 for NOP forms and sections 3.3 on p.50 and C.1 on p.303 for instruction encodings. Archived from the [http://ftp.digital.com:80/pub/Digital/DECinfo/semiconductor/literature/alphaahb.pdf original] on 27 Aug 2004.</ref>
|-
| <code>FNOP</code>
| 4
| 0x5FFF041F
| Floating-point NOP. Opcode for <code>CPYS f31,f31,f31</code>, an instruction that performs copy-sign with the always-0 register as source for both sign and exponent/mantissa, and stores the result in the always-0 register.<ref name="alpha_handbook4" />
|-
| <code>UNOP</code>
| 4
| 0x2FFE0000
| Universal NOP. Opcode for <code>LDQ_U r31,0($sp)</code>. The LDQ_U (unaligned load) opcode is, on 21164 and later, special-cased so that when used with the always-0 register as a destination register, no memory access is performed.<ref name="alpha_handbook4" /><ref>JH Edmondson et al, [https://acg.cis.upenn.edu/milom/cis501-Fall09/papers/Alpha21164.pdf Superscalar Instruction Execution in the 21164 Alpha Microprocessor], April 1995, p.6. [https://web.archive.org/web/20230105163822/https://acg.cis.upenn.edu/milom/cis501-Fall09/papers/Alpha21164.pdf Archived] on 5 Jan 2023.</ref> The address register and displacement may take any value, but is most commonly given as <code>0($sp)</code> which is [[Stack register|stack pointer]] + zero.<ref>Digital, [https://web.archive.org/web/20001001010701/http://www.unix.digital.com:80/faqs/publications/base_doc/DOCUMENTATION/V40E_PDF/APS31DTE.PDF Digital UNIX Assembly Language Programmer’s Guide], order no. AA-PS31D-TE, March 1996, see section C.7 on p.219. Archived from the [http://www.unix.digital.com/faqs/publications/base_doc/DOCUMENTATION/V40E_PDF/APS31DTE.PDF original] on 1 Oct 2000.</ref>
|-
| [[AMD 29k]]
| <code>NOP</code>
| 4
| 0x70400101
| Opcode for <code>aseq 0x40,gr1,gr1</code>, an instruction that asserts that the [[stack register]] is equal to itself.<ref>AMD, {{cite web |url=http://www.bitsavers.org/components/amd/Am29000/1991_AMD_29050_Users_Manual.pdf |title=Am29050 Microprocessor User's Manual |date=1991 |pages=223,257}}</ref>
|-
| [[AVR microcontrollers|AVR]]
| <code>NOP</code>
| 2
| 0x0000
| one clock cycle
|-
| [[COP400]]
| <code>NOP</code>
| 1
| 0x44
|
|-
| [[COP8]]
| <code>NOP</code>
| 1
| 0xB8
|
|-
| rowspan=2 | {{nowrap|[[IBM System/360]],}} {{nowrap|[[IBM System/370]],}} {{nowrap|[[IBM System/390]],}} {{nowrap|[[z/Architecture]],}} {{nowrap|[[UNIVAC Series 90]]}}
| <code>NOP</code>
| 4
| 0x47000000 or 0x470nnnnn or 0x47n0nnnn where "n" is any 4-bit value.
|rowspan=2| The NOP ("No-Op") and NOPR ("No-Op Register") are a subset of the "Branch on Condition" or "Branch on Condition Register" instructions, respectively; both versions have two options for generating a NO-OP. 
In the case of both the NOP and NOPR instructions, the first 0 in the second byte is the "mask" value, the condition to test such as equal, not equal, high, low, etc. If the mask is 0, no branch occurs. 

In the case of the NOPR instruction, the second value in the second byte is the register to branch on. If register 0 is chosen, no branch occurs regardless of the mask value. Thus, if either of the two values in the second byte is 0, the branch will not happen. If the first 0 in the second byte is 0, the value of the second value in the second byte is irrelevant on most processors; however, on the [[IBM System/360 Model 91]], if that value refers to register 15, the instruction will wait for all previously-decoded instructions to complete before continuing.<ref>{{cite web |series=Systems Reference Library |title=IBM System/360 Model 91 Functional Characteristics |url=http://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6907-2_360-91_funcChar.pdf |page=16 |publisher=IBM |access-date=17 January 2025}}</ref>

In the case of the NOP instruction, the second value in the second byte is the "base" register of a combined base register, displacement register and offset address. If the base register is also 0, the branch is not taken regardless of the value of the displacement register or displacement address.
|-
| <code>NOPR</code>
| 2
| 0x0700 or 0x070n or 0x07n0 where "n" is any 4-bit value.
|-
| [[LoongArch]]
| <code>NOP</code>
| 4
| 0x03400000
| Opcode for <code>andi r0,r0,0</code>, an instruction that bitwise-ANDs the always-0 register with zero.<ref>{{cite book |publisher=Loongson |url=https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.pdf |title=LoongArch Reference Manual, Volume 1: Basic Architecture, version 1.10 |at=Section 2.2.1.10 on page 23 and appendix B on page 190}}</ref>
|-
| [[MIPS architecture|MIPS]]
| <code>NOP</code>
| 4
| 0x00000000
| Stands for <code>sll r0,r0,0</code>, meaning: Logically shift register 0 zero bits to the left and store the result in register 0. Writes to register 0 are ignored; it always contains 0.
|-
| [[MIPS-X]]
| <code>NOP</code>
| 4
| 0x60000019
| (extended opcode for <code>add r0,r0,r0</code>)
|-
| [[MIX (abstract machine)|MIX]]
| <code>NOP</code>
| 1 word
| ± * * * * 0
| The * bytes are arbitrary, and can be anything from 0 to the maximum byte (required to be in the range 63-99). MIX uses sign-magnitude representation.
|-
|  [[MMIX]]
| <code>SWYM</code>
| 4
| 0xFD******
| SWYM stands for "Sympathize with your machinery". The * digits can be chosen arbitrarily.
|-
| [[MOS Technology 65xx]] (e.g. [[6502]])
| <code>NOP</code>
| 1
| 0xEA
| NOP consumes two clock cycles. [[Illegal opcode|Undefined opcodes]] in the [[NMOS logic|NMOS]] versions of the 65xx family were converted to be NOPs of varying instruction lengths and cycle times in the [[WDC 65C02|65C02]].
|-
| [[Motorola 6800]]
| <code>NOP</code>
| 1
| 0x01
|
|-
| rowspan=2 | [[Motorola 68000 family]]
| <code>NOP</code>
| 2
| 0x4E71
| This synchronizes the [[Pipeline (computing)|pipeline]] and prevents instruction overlap.{{r|m68ref|p1=3-21|m68ref|p2=4-147}}
|-
| <code>TRAPF</code>,<br/>{{nowrap|<code>TRAPF.W #data</code>,}}<br/><code>TRAPF.L #data</code>
| 2,<br/>4,<br/>6
| 0x51FC,<br/>{{nowrap|0x51FA 0xnnnn,}}<br/>{{nowrap|0x51FB 0xnnnn 0xnnnn}}
| Trap if false.

Suggested opcode for [[Motorola 68020|68020]] and later 68k processors if a NOP without pipeline synchronization is desired. ('n' may take any 4-bit value.){{r|m68ref|p1=3-21|m68ref|p2=4-189}}
|-
| [[Motorola 6809]]
| <code>NOP</code>
| 1
| 0x12
|
|-
| [[Motorola 88000]] family
| <code>BCND lt0,r0,X</code>,<br/><code>ADD r0,r0,r0</code>,<br/><code>TB1 0,r0,x</code>
| 4
| 0xE980xxxx,<br/>0xF4007000,<br/>0xF000D8xx
| Branch if always-0 register is less than 0,<br/>Add always-0 register to itself,<br/>Trap if bit 0 of always-0 register is 1 (serializing).<ref>Motorola, [https://archive.computerhistory.org/resources/access/text/2024/03/102793158-05-01-acc.pdf MC88110 32-bit Microprocessor Design Specification, Revision 2.0] - see section 2.1.2.3 on page 11 for a listing of recommended NOPs, and pages 10, 170 and 171 for instruction encodings. [https://web.archive.org/web/20250319183030/https://archive.computerhistory.org/resources/access/text/2024/03/102793158-05-01-acc.pdf Archived] on 19 Mar 2025.</ref>
|-
| [[MSP430]]
| <code>NOP</code>
| 2
| 0x4303
| Opcode for <code>mov #0,r3</code> or <code>mov r3,r3</code>, an instruction that performs a move from a "constant generation register" to itself.<ref>Texas Instruments, [https://www.ti.com/lit/ug/slau144k/slau144k.pdf MSP430F2xx, MSP430G2xx Family User's Guide], Dec 2004, sections 3.24 on page 47, 3.4.5 on page 63, 3.4.6.33 on page 98. [https://web.archive.org/web/20220901044506/https://www.ti.com/lit/ug/slau144k/slau144k.pdf Archived] on 1 Sep 2022.</ref>
|-
| rowspan=2 | [[PA-RISC]]
| <code>NOP</code>
| 4
| 0x08000240
| Opcode for <code>OR 0,0,0</code>.<ref name="parisc_nop"/>
|-
| <code>LDI 26,0</code>
| 4
| 0x34000034
| Palindromic NOP - that is, an instruction that executes as NOP regardless of whether byte order is interpreted as [[Endianness|little-endian or big-endian]]. Some PA-RISC system instructions are required to be followed by seven palindromic NOPs.<ref name="parisc_nop">{{cite book |publisher=[[Hewlett-Packard]] |url=https://parisc.wiki.kernel.org/images-parisc/7/73/Parisc2.0.pdf |title=PA-RISC 2.0 Architecture |date=1995 |pages=2{{hyp}}21,7{{hyp}}103 |archive-url=https://web.archive.org/web/20200621164851/https://parisc.wiki.kernel.org/images-parisc/7/73/Parisc2.0.pdf |archive-date=June 21, 2020 |url-status=dead}}</ref>
|-
| [[PDP-10]]
| <code>JFCL 0,</code> (conventional)<br><code>JUMP, SETA, SETAI, CAI, TRN, TLN</code>
| 1 word
| 25500******* (octal)
| Jump never<br>Jump never, set nothing, skip never
|-
| [[PDP-11 architecture|PDP-11]]
| <code>NOP</code>
| 2
| 000240 (octal)
| Clear none of the condition codes
|-
| [[PIC microcontroller]]
| <code>NOP</code>
| 12 bits
| 0b000000000000
|
|-
| [[IBM POWER architecture|POWER]], [[PowerPC]], [[Power ISA]]
| <code>NOP</code>
| 4
| 0x60000000
| Opcode for <code>ori r0,r0,0</code>.

Under the Power ISA, many apparent no-op instruction encodings have significant side-effects − therefore, no-op encodings other than {{nowrap|<code>ori r0,r0,0</code>}} should be carefully avoided unless these side-effects are specifically intended. For example:<ref>{{cite book |publisher=OpenPOWER Foundation |url=https://files.openpower.foundation/s/9izgC5Rogi5Ywmm/download/OPF_PowerISA_v3.1C.pdf |title=Power ISA version 3.1C |date=26 May 2024 |at=Book 1 section 3.3.13 on pages 97-99; book 2 section 3.2 on page 987 and section 4.3.3 on page 1005; book 3 section 5.4.3 on page 1100, section 9.2.1 on page 1244 and section 11.3 on page 1253 |archive-url=https://web.archive.org/web/20240910155728/https://files.openpower.foundation/s/9izgC5Rogi5Ywmm/download/OPF_PowerISA_v3.1C.pdf |archive-date=10 September 2024 |url-status=dead}}</ref>
* <code>ori r31,r31,0</code> is a serializing instruction.
* <code>or rX,rX,rX</code> with X=1,2,3,5,6,7 or 31 sets thread priority based on X.
* <code>or r26,r26,r26</code> is a memory store writeback hint.
* <code>xori r0,r0,0</code> is an explicitly unoptimized no-op for use in timing-loops.
* <code>and rX,rX,rX</code> with X=0,1 are performance-probe no-ops.
* <code>or rX,rX,rX</code> with X=28,29,30,31 will stall instruction dispatch for a fixed number of CPU cycles on IBM [[Power Processing Element|PPE]] based processors.<ref>IBM, [http://ilab.usc.edu/packages/cell-processor/docs/CBE_Handbook_v1.1_24APR2007_pub.pdf Cell Broadband Engine Programming Handbook], version 1.1, 24 Apr 2007, section 10.6.2.2 on page 316. [https://web.archive.org/web/20080524084600/http://ilab.usc.edu/packages/cell-processor/docs/CBE_Handbook_v1.1_24APR2007_pub.pdf Archived] on 24 May 2008.</ref>
* <code> ori rX,rX,0</code> with X=1,2 are "group ending NOP"s in some [[IBM Power microprocessors|POWER CPUs]]<ref>IBM, [https://support.scinet.utoronto.ca/Tutorials/compiler-workshop/Compiling_for_POWER6.pdf SCINET Briefing: Compiling for Power6], Feb 2009, slide 9. [https://web.archive.org/web/20250323031022/https://support.scinet.utoronto.ca/Tutorials/compiler-workshop/Compiling_for_POWER6.pdf Archived] on 23 Mar 2025</ref><ref>{{cite book |publisher=[[IBM]] |url=https://www.setphaserstostun.org/power8/POWER8_UM_v1.3_16MAR2016_pub.pdf |title=POWER8 Processor User's Manual for the Single-Chip Modul, version 1.3 |date=16 March 2016 |at=Section 10.1.8 on page 209 |archive-url=https://web.archive.org/web/20181228110025/https://www.setphaserstostun.org/power8/POWER8_UM_v1.3_16MAR2016_pub.pdf |archive-date=28 December 2018 |url-status=live}}</ref>
|-
| rowspan=2 | [[RISC-V]]
| <code>NOP</code>
| 4
| 0x00000013
| <code>ADDI x0, x0, 0</code>
|-
| <code>C.NOP</code>
| 2
| 0x0001
| <code>C.ADDI x0, 0</code>. Only available on RISC-V CPUs that support the "C" (compressed instructions) extension.<ref>{{cite book |publisher=[[RISC-V Foundation]] |url=https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf |title=The RISC-V Instruction Set Manual, Volume 1: User-Level ISA, version 2.2 |date=7 May 2017 |page=79}}</ref>
|-
| [[Signetics 8X300]]
| <code>MOV AUX, AUX</code>
| 16 bits
| 0x0000
| Move AUX to AUX with no rotate
|-
| [[SPARC]]
| <code>NOP</code>
| 4
| 0x01000000
| Stands for <code>sethi 0, %g0</code> which zeroes the hardwired-to-zero <code>%g0</code> register<ref>{{cite book
 |url          = http://www.sparc.org/standards/SPARCV9.pdf
 |title        = The SPARC Architecture Manual, Version 9
 |editor       = Weaver, D. L.
 |editor2      = Germond, T.
 |publisher    = [[Prentice Hall]]
 |isbn         = 0-13-825001-4
 |year         = 1994
 |quote        = Note that NOP is a special case of the SETHI instruction, with imm22 = 0 and rd = 0.
 |access-date   = 2014-01-09
 |archive-url  = https://web.archive.org/web/20120118213535/http://www.sparc.org/standards/SPARCV9.pdf
 |archive-date = 2012-01-18
 |url-status      = dead
}}</ref>
|-
| rowspan=2 | Sunplus S+core
| <code>NOP</code>
| 4
| 0x80008000
| rowspan=2 | Architectural NOPs<ref>Sunplus Technology Co. Ltd, [https://web.archive.org/web/20121115095302/http://raidenii.net:80/files/datasheets/cpu/s_core7.pdf S+core7 Programming Guide], v1.4, 22 Mar 2007, pages 12, 90 and 166. Archived from the [http://raidenii.net/files/datasheets/cpu/s_core7.pdf original] on 15 Nov 2012.</ref>
|-
| <code>NOP!</code>
| 2
| 0x0000
|-
| rowspan=2 | [[SuperH]]
| <code>NOP</code>
| 2
| 0x0009
| <ref>SuperH Inc. [https://web.archive.org/web/20090320050552/http://lars.nocrew.org:80/computers/processors/SuperH/cpush5v3.pdf SH-5 CPU Core, Volume 3: SHcompact], 22 Feb 2002, page 219. Archived from the [http://lars.nocrew.org:80/computers/processors/SuperH/cpush5v3.pdf original] on 20 Mar 2009.</ref>
|-
| <code>NOP</code>
| 4
| 0x6FF0FFF0
| 32-bit NOP, present on SH-5 only.<ref>SuperH Inc. [https://web.archive.org/web/20090320050550/http://lars.nocrew.org:80/computers/processors/SuperH/cpush5v2.pdf SH-5 CPU Core, Volume 2: SHmedia], 22 Feb 2000, page 260. Archived from the [http://lars.nocrew.org:80/computers/processors/SuperH/cpush5v2.pdf original] on 20 Mar 2009.</ref>
|-
| rowspan=2 | [[Tensilica]] Xtensa
| <code>NOP</code>, <code>_NOP</code>
| 3
| 0x0020F0
| rowspan=2 | Assemblers may convert "NOP" to "NOP.N" - the "_NOP" mnemonic (with a leading underscore) can be used to prevent such conversion.<ref>Tensilica, [https://0x04.net/~mwk/doc/xtensa.pdf Xtensa Instruction Set Architecture Reference Manual], Apr 2010, pages 459 and 460. [https://web.archive.org/web/20160305050930/https://0x04.net/~mwk/doc/xtensa.pdf Archived] on 5 Mar 2016.</ref>
|-
| <code>NOP.N</code>
| 2
| 0xF03D
|-
| [[VAX]]
| <code>NOP</code>
| 1
| 0x01
| Delay is dependent on processor type
|-
| [[WD16]]
| <code>NOP</code>
| 2
| 0x0000
|
|}

From a hardware design point of view, unmapped areas of a bus are often designed to return zeroes; since the [[NOP slide]] behavior is often desirable, it gives a bias to coding it with the all-zeroes opcode.