Editing Nano-RAM (section)

==Technology==
The first generation Nantero NRAM technology was based on a three-terminal [[semiconductor device]] where a third terminal is used to switch the memory cell between memory states.  The second generation NRAM technology is based on a two-terminal memory cell. The two-terminal cell has advantages such as a smaller cell size, better scalability to sub-20&nbsp;nm nodes (see [[semiconductor device fabrication]]), and the ability to [[Passivation (chemistry)|passivate]] the memory cell during fabrication.

In a non-woven fabric matrix of [[carbon nanotubes]] (CNTs), crossed nanotubes can either be touching or slightly separated depending on their position.  When touching, the carbon nanotubes are held together by [[Van der Waals forces]].<ref>{{cite web | url=https://semiengineering.com/what-is-drams-future/ | title=What is DRAM's Future? | date=9 April 2020 }}</ref>  Each NRAM "cell" consists of an interlinked network of CNTs located between two electrodes as illustrated in Figure 1.  The CNT fabric is located between two metal electrodes, which is defined and etched by [[photolithography]], and forms the NRAM cell.

[[File:NRAM fabric.png |thumb|upright=1.4 |Carbon nanotube fabric]]

The NRAM acts as a resistive non-volatile [[random-access memory]] (RAM) and can be placed in two or more resistive modes depending on the resistive state of the CNT fabric.  When the CNTs are not in contact the [[Electrical resistance|resistance]] state of the fabric is high and represents an "off" or "0" state.  When the CNTs are brought into contact, the resistance state of the fabric is low and represents an "on" or "1" state.  NRAM acts as a memory because the two resistive states are very stable.   In the 0 state, the CNTs (or a portion of them) are not in contact and remain in a separated state due to the stiffness of the CNTs resulting in a high resistance or low  current measurement state between the top and bottom electrodes.   In the 1 state, the CNTs (or a portion of them) are in contact and remain contacted due to Van der Waals forces between the CNTs, resulting in a low resistance or high current measurement state between the top and bottom electrodes. Note that other sources of resistance such as contact resistance between electrode and CNT can be significant and also need to be considered.

To switch the NRAM between states, a small voltage greater than the read voltage is applied between top and bottom electrodes.  If the NRAM is in the 0 state, the voltage applied will cause an electrostatic attraction between the CNTs close to each other causing a SET operation.  After the applied voltage is removed, the CNTs remain in a 1 or low resistance state due to physical adhesion (Van der Waals force) with an [[activation energy]] (E<sub>a</sub>) of approximately 5eV.  If the NRAM cell is in the 1 state, applying a voltage greater than the read voltage will generate CNT phonon excitations with sufficient energy to separate the CNT junctions.  This is the phonon driven RESET operation.    The CNTs remain in the OFF or high resistance state due to the high mechanical stiffness ([[Young's Modulus]] 1 TPa) with an activation energy (E<sub>a</sub>) much greater than 5 eV.  Figure 2 illustrates both states of an individual pair of CNTs involved in the switch operation. Due to the high activation energy (> 5eV) required for switching between states, the NRAM switch resists outside interference like radiation and [[operating temperature]] that can erase or flip conventional memories like [[DRAM]].

[[File:NRAM contact point.png|thumb|Figure 2: Carbon nanotube contact points]]

NRAMs are fabricated by depositing a uniform layer of CNTs onto a prefabricated array of drivers such as transistors as shown in Figure 1. The bottom electrode of the NRAM cell is in contact with the underlying [[via (electronics)]] connecting the cell to the driver.  The bottom electrode may be fabricated as part of the underlying via or it may be fabricated simultaneously with the NRAM cell, when the cell is photolithographically defined and etched.   Before the cell is photolithographically defined and etched, the top electrode is deposited as a metal film onto the CNT layer so that the top metal electrode is patterned and etched during the definition of the NRAM cell.   Following the dielectric passivation and fill of the array, the top metal electrode is exposed by etching back the overlying dielectric using a smoothing process such as [[chemical-mechanical planarization]].  With the top electrode exposed, the next level of metal wiring interconnect is fabricated to complete the NRAM array.   Figure 3 illustrates one circuit method to select a single cell for writing and reading. Using a cross-grid interconnect arrangement, the NRAM and driver, (the cell), forms a memory array similar to other memory arrays.  A single cell can be selected by applying the proper voltages to the word line (WL), bit line (BL), and select lines (SL) without disturbing the other cells in the array. Alternatively between the bottom electrode and top metal layer they may be two layers of CNTs: one with uniformly arranged CNTs, and another with randomly arranged CNTs. The uniformly arranged CNTs are used to protect the randomly arranged CNTs from the top metal layer.<ref>{{cite web | url=https://semiengineering.com/what-is-drams-future/ | title=What is DRAM's Future? | date=9 April 2020 }}</ref>

[[File:CNT switch.svg|thumb|Figure 3: CNT switch]]