Editing Network processor (section)

==History of development==
In modern [[telecommunications network]]s, information (voice, video, data) is transferred as [[Packet (information technology)|packet]] data (termed [[packet switching]]) which is in contrast to older telecommunications networks that carried information as [[analog signal]]s such as in the [[public switched telephone network]] (PSTN) or analog [[TV]]/[[Radio]] networks. The processing of these packets has resulted in the creation of [[integrated circuit]]s (IC) that are optimised to deal with this form of packet data. Network processors have specific features or architectures that are provided to enhance and optimise packet processing within these networks.

Network processors have evolved into ICs with specific functions. This evolution has resulted in more complex and more flexible ICs being created. The newer circuits are programmable and thus allow a single [[computer hardware|hardware]] IC design to undertake a number of different functions, where the appropriate [[software]] is installed.

Network processors are used in the manufacture of many different types of [[Networking hardware|network equipment]] such as:

* [[Router (computing)|Router]]s, [[software router]]s and [[Network switch|switches]] ([[Inter-network processors]])
* [[Firewall (networking)|Firewall]]s
* [[Session border controller]]s
* [[Intrusion detection system|Intrusion detection devices]]
* [[Intrusion prevention system|Intrusion prevention devices]]
* [[Network monitoring]] systems
* [[Network security]] ([[secure cryptoprocessor]]s)

=== Reconfigurable Match-Tables ===
Reconfigurable Match-Tables<ref>{{Cite journal |last1=Bosshart |first1=Pat |last2=Gibb |first2=Glen |last3=Kim |first3=Hun-Seok |last4=Varghese |first4=George |last5=McKeown |first5=Nick |last6=Izzard |first6=Martin |last7=Mujica |first7=Fernando |last8=Horowitz |first8=Mark |date=2013-08-01 |title=Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN |url=https://www.microsoft.com/en-us/research/publication/forwarding-metamorphosis-fast-programmable-match-action-processing-in-hardware-for-sdn/ |language=en-US}}</ref><ref name=":0">{{Cite book |last1=Gibb |first1=Glen |last2=Varghese |first2=George |last3=Horowitz |first3=Mark |last4=McKeown |first4=Nick |title=Architectures for Networking and Communications Systems |chapter=Design principles for packet parsers |date=October 2013 |chapter-url=https://ieeexplore.ieee.org/document/6665172 |pages=13–24 |doi=10.1109/ANCS.2013.6665172|isbn=978-1-4799-1641-2 |s2cid=12282067 }}</ref> were introduced in 2013 to allow switches to operate at high speeds while maintaining flexibility when it comes to the network protocols running on them, or the processing to does to them. [[P4 (programming language)|P4]]<ref>{{Cite web |title=P4: Programming Protocol-Independent Packet Processors {{!}} acm sigcomm |url=https://www.sigcomm.org/node/3503 |access-date=2022-03-26 |website=www.sigcomm.org |language=en}}</ref> is used to program the chips. The company [[Barefoot Networks]] was based around these processors and was later purchased by [[Intel]] in 2019.
[[File:RMT Fig.svg|thumb|RMP Pipeline Description]]
An RMT pipeline relies on three main stages; the programmable parser,<ref name=":0" /> the Match-Action tables and the programmable deparser. The parser reads the packet in chunks and processes these chunks to find out which protocols are used in the packet ([[Ethernet frame|Ethernet]], [[IEEE 802.1Q|VLAN]], [[IPv4]]...) and extracts certain fields from the packet into the Packet Header Vector (PHV). Certain fields in the PHV may be reserved for special uses such as present headers or total packet length. The protocols are typically programmable, and so are the fields to extract. The Match-Action tables are a series of units that read an input PHV, match certain fields in it using a [[Crossbar switch|crossbar]] and [[Content-addressable memory|CAM memory]], the result is a wide instruction that operates on one or more fields of the PHV and data to support this instruction. The output PHV is then sent to the next MA stage or to the deparser. The deparser takes in the PHV as well as the original packet and its metadata (to fill in missing bits that weren't extracted into the PHV) and then outputs the modified packet as chunks. It's typically programmable as with the parser and may reuse some of the configuration files.

FlexNIC<ref>{{Cite book |last1=Kaufmann |first1=Antoine |last2=Peter |first2=SImon |last3=Sharma |first3=Naveen Kr. |last4=Anderson |first4=Thomas |last5=Krishnamurthy |first5=Arvind |title=Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems |chapter=High Performance Packet Processing with FlexNIC |date=2016-03-25 |series=ASPLOS '16 |location=New York, NY, USA |publisher=Association for Computing Machinery |pages=67–81 |doi=10.1145/2872362.2872367 |isbn=978-1-4503-4091-5|s2cid=9625891 |doi-access=free }}</ref> attempts to apply this model to [[Network interface controller|Network Interface Controllers]] allowing servers to send and receive packets at high speeds while maintaining protocol flexibility and without increasing the CPU overhead.