Editing Nios II (section)

==Key features==
Like the original Nios, the Nios II architecture is a [[RISC]] [[Soft microprocessor|soft-core]] architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full [[32-bit_computing|32-bit]] design:

* 32 general-purpose 32-bit registers,
* Full 32-bit instruction set, data path, and address space,
* Single-instruction 32 × 32 multiply and divide producing a 32-bit result.

The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by, for example, adding a predefined memory management unit, or defining custom instructions and custom peripherals.

=== Custom instructions ===
Similar to native Nios II instructions, user-defined instructions accept values from up to two 32-[[bit]] source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in [[C (programming language)|C]].

=== Custom peripherals ===
For performance-critical systems that spend most CPU cycles executing a specific section of code, a user-defined peripheral can potentially offload part or all of the execution of a software-algorithm to user-defined [[hardware logic]], improving power-efficiency or application throughput.

=== Memory Management Unit ===
Introduced with [[Altera Quartus|Quartus]] 8.0, the optional MMU enables Nios II to run operating systems which require hardware-based paging and protection, such as the Linux kernel. Without an MMU, Nios is restricted to operating systems which use a simplified protection and virtual memory-model: e.g., [[μClinux]] and [[FreeRTOS]].

=== Memory Protection Unit ===
Introduced with Quartus 8.0, the optional MPU provides memory protection similar to that provided by an MMU but with a simpler programming model and without the performance overhead associated with an MMU.