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OpenRISC
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==Instruction set== The instruction set is a reasonably simple traditional RISC architecture reminiscent of [[MIPS architecture|MIPS]] using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors. Another notable feature is a rich set of ''single instruction, multiple data'' ([[SIMD]]) instructions intended for [[digital signal processing]].
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