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==History== ===Background and motivation=== [[File:dualportintelmtpro1000mtserveradapterspc.jpg|thumb|A Dual Port [[Gigabit Ethernet]] [[Network Card]] for single PCI-X slot to save on PCI-X slots and use the full potential of the PCI-X [[64-bit computing|64-bit]] bus.]] [[File:LSI Logic MegaRAID SATA 300-8X SATA RAID controller.jpg|thumb|A 8 port [[SATA]] [[host bus adapter]] for PCI-X from [[Lsi logic]].]] [[File:HP VISUALIZE fx10 Pro (A1299-6503) front.jpg|thumb|HP VISUALIZE fx10 Pro [[video card]] for PCI-X]] In PCI, a transaction that cannot be completed immediately is postponed by either the target or the initiator issuing retry-cycles, during which no other agents can use the PCI bus. Since PCI lacks a split-response mechanism to permit the target to return data at a later time, the bus remains occupied by the target issuing retry-cycles until the read data is ready. In PCI-X, after the master issues the request, it disconnects from the PCI bus, allowing other agents to use the bus. The split-response containing the requested data is generated only when the target is ready to return all of the requested data. Split-responses increase bus efficiency by eliminating retry-cycles, during which no data can be transferred across the bus. PCI also suffered from the relative scarcity of unique interrupt lines. With only 4 interrupt pins (INT A/B/C/D), systems with many PCI devices require multiple functions to share an interrupt line, complicating host-side interrupt-handling. PCI-X added [[Message Signaled Interrupts]], an interrupt system using writes to host-memory. In MSI-mode, the function's interrupt is not signaled by asserting an INTx line. Instead, the function performs a memory-write to a system-configured region in host-memory. Since the content and address are configured on a per-function basis, MSI-mode interrupts are dedicated instead of shared. A PCI-X system allows both MSI-mode interrupts and legacy INTx interrupts to be used simultaneously (though not by the same function). The lack of registered I/Os limited PCI to a maximum frequency of 66 MHz. PCI-X I/Os are registered to the PCI clock, usually through means of a PLL to actively control I/O delay the bus pins. The improvement in setup time allows an increase in frequency to 133 MHz. Some devices, most notably Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and cluster interconnects could by themselves saturate the PCI bus's 133 MB/s bandwidth. Ports using a bus speed doubled to 66 MHz and a bus width doubled to 64 bits (with the pin count increased to 184 from 124), in combination or not, have been implemented. These extensions were loosely supported as optional parts of the PCI 2.x standards, but device compatibility beyond the basic 133 MB/s continued to be difficult. Developers eventually used the combined 64-bit and 66-MHz extension as a foundation, and, anticipating future needs, established 66-MHz and 133-MHz variants with a maximum bandwidth of 532 MB/s and 1064 MB/s respectively. The joint result was submitted as PCI-X to the [[PCI-SIG|PCI Special Interest Group]] ([[Special Interest Group]] of the [[Association for Computing Machinery]]). Subsequent approval made it an [[open standard]] adoptable by all computer developers. The PCI SIG controls technical support, training, and compliance testing for PCI-X. IBM, Intel, Microelectronics, and [[Mylex]] were to develop supporting chipsets. [[3Com]] and [[Adaptec]] were to develop compatible peripherals. To accelerate PCI-X adoption by the industry, Compaq offered PCI-X development tools at their Web site. ===PCI-X 1.0=== The PCI-X standard was developed jointly by [[IBM]], [[Hewlett-Packard|HP]], and [[Compaq]] and submitted for approval in 1998. It was an effort to codify proprietary [[Server (computing)|server]] extensions to the [[PCI local bus]] to address several shortcomings in PCI, and increase performance of high bandwidth devices, such as Gigabit Ethernet, [[Fibre Channel]], and [[SCSI|Ultra3 SCSI]] cards, and allow processors to be interconnected in [[Computer cluster|clusters]]. Intel gave only a qualified welcome to PCI-X, stressing that the next generation bus would have to be a "fundamentally new architecture".<ref>{{cite news |title=PCI-X Gang of Three challenges Intel with Future I/O |url=https://www.theregister.co.uk/1999/01/13/pcix_gang_of_three_challenges/ |date=1999-01-13 |first= John |last=Lettice |journal=The Register}}</ref> Without Intel's support, PCI-X failed to be adopted in PCs. According to Rick Merritt of the EE Times, "A falling-out between the PCI SIG and a key Intel interconnect designer who spearheaded development on the [[Accelerated Graphics Port]] caused Intel to pull out of the initial PCI-X effort".<ref>{{cite news |url=http://www.eetimes.com/document.asp?doc_id=1204479 |title=Servers gas up with 4-Gbyte/s PCI-X 2.0 spec |first=Rick |last=Merritt |date=2001-11-21 |journal=EE Times}}</ref> The PCI-X interface was however briefly adopted by Apple, for the first few generations of the [[Power Macintosh G5]]. The first PCI-X products were manufactured in 1998, such as the Adaptec AHA-3950U2B dual Ultra2 Wide SCSI controller, however at that point the PCI-X connector was merely referred to as "64-bit ready PCI" on packaging, hinting at future [[forward compatibility]]. Actual PCI-X branding only became standard later, likely coinciding with widespread availability of PCI-X equipped motherboards. When more details of PCI Express were released in August 2001, PCI SIG chairman Roger Tipley expressed his belief that "PCI-X is going to be in servers forever because it serves a certain level of functionality, and it may not be compelling to switch to 3GIO [PCI Express] for that functionality. We learned that from not being able to get rid of ISA. ISA hung around because of all of these systems that weren't high-volume parts." Tipley also announced that (at the time) the PCI SIG was planning to fold PCI Express and PCI-X 2.0 into a single work tentatively called PCI 3.0,<ref>Jerry Ascierto (8/30/2001) "[http://www.eetimes.com/document.asp?doc_id=1228264 Intel details next-generation I/O spec]", ''EE Times''</ref> but that name was eventually used for a relatively minor revision of conventional PCI.<ref>{{Cite web |url=http://www.pcisig.com/news_room/faqs/faq_pci30/pci30_faq.pdf |title=Archived copy |access-date=2013-12-16 |archive-date=2014-02-11 |archive-url=https://web.archive.org/web/20140211033021/http://www.pcisig.com/news_room/faqs/faq_pci30/pci30_faq.pdf |url-status=dead }}</ref> ===PCI-X 2.0=== In 2003, the PCI SIG ratified PCI-X 2.0. It adds 266-MHz and 533-MHz variants, yielding roughly 2,132 MB/s and 4,266 MB/s throughput, respectively. PCI-X 2.0 makes additional protocol revisions that are designed to help system reliability and add [[Error-correcting code]]s to the bus to avoid re-sends.<ref name="PCI-SIG">{{cite web|url=http://www.pcisig.com/news_room/faqs/faq_20/|title=PCI-SIG β FAQ β PCI-X 2.0|access-date=2008-02-17|archive-date=2008-02-15|archive-url=https://web.archive.org/web/20080215215940/http://www.pcisig.com/news_room/faqs/faq_20/|url-status=dead}}</ref> To deal with one of the most common complaints of the PCI-X form factor, the 184-pin connector, 16-bit ports were developed to allow PCI-X to be used in devices with tight space constraints. Similar to PCI-Express, PtP functions were added to allow for devices on the bus to talk to each other without burdening the [[Central processing unit|CPU]] or bus controller. Despite the various theoretical advantages of PCI-X 2.0 and its backward compatibility with PCI-X and PCI devices, it has not been implemented on a large scale ({{as of|2008|lc=y}}). This lack of implementation primarily is because hardware vendors have chosen to integrate [[PCI Express]] instead. [[IBM]] was one of the (few) vendors which provided PCI-X 2.0 (266 MHz) support in their [[IBM AS/400|System i5]] Model 515, 520 and 525; IBM advertised these slots as suitable for [[10 Gigabit Ethernet]] adapters, which they also provided.<ref>{{cite web|url=http://www.redbooks.ibm.com/redpapers/pdfs/redp4011.pdf|quote="A third generation of PCI is now offered with the introduction of the 1.9 GHz System i5 Models 515, 520, and 525. These models have a PCI-X DDR (PCI-X 2.0) slot that runs at a maximum of 266 MHz and supports only adapters that can run without an IOP. This slot is ideally suited for ultra-high bandwidth adapters such as the new 266 MHz (DDR) #5721/#5722 10 Gb Ethernet adapters."|page=7|title=PCI, PCI-X, PCI-X DDR, and PCIe Placement Rules for IBM System i Models}}</ref> [[Hewlett-Packard|HP]] offered PCI-X 2.0 in some [[ProLiant]] and [[HPE Integrity Servers|Integrity]] servers and offered dual-port 4 Gbit/s [[Fibre Channel]] adapters, also operating at 266 MHz.<ref>{{Cite web |url=http://h18004.www1.hp.com/products/quickspecs/12481_na/12481_na.PDF |title=HP FC2243 Dual Channel 4Gb PCI-X 2.0 HBA |access-date=2013-12-16 |archive-date=2013-12-16 |archive-url=https://web.archive.org/web/20131216060927/http://h18004.www1.hp.com/products/quickspecs/12481_na/12481_na.PDF |url-status=dead }}</ref> [[AMD]] supported PCI-X 2.0 (266 MHz) via its 8132 [[Hypertransport]] to PCI-X 2.0 tunnel chip.<ref>{{cite web|url=http://www.theinquirer.net/inquirer/news/1016137/amd-rolls-out-8132-pci-x-tunnel-part |archive-url=https://web.archive.org/web/20131216104651/http://www.theinquirer.net/inquirer/news/1016137/amd-rolls-out-8132-pci-x-tunnel-part |url-status=unfit |archive-date=December 16, 2013 |title=AMD rolls out 8132 PCI-X tunnel part |publisher=The Inquirer |date=2004-06-14 |access-date=2014-02-13}}</ref><ref name="MuellerSoper2006">{{cite book|author1=Scott M. Mueller|author2=Mark Edward Soper|author3=Barrie Sosinsky|title=Upgrading and Repairing Servers|url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT366|year=2006|publisher=Pearson Education|isbn=978-0-13-279698-9|page=366}}</ref> [[ServerWorks]] was a vocal supporter of PCI-X 2.0<ref>{{cite web |url=http://serverworks.com/technology/pdf/PCI-X_2-0_WhitePaper.pdf |title=Archived copy |website=serverworks.com |access-date=12 January 2022 |archive-url=https://web.archive.org/web/20030718015904/http://serverworks.com/technology/pdf/PCI-X_2-0_WhitePaper.pdf |archive-date=18 July 2003 |url-status=dead}}</ref> (to the detriment of the first generation PCI Express) particularly through its chief [[Raju Vegesna]],<ref>[http://www.eetimes.com/document.asp?doc_id=1144859 ServerWorks chief spurns first-generation PCI Express]</ref> who was however fired soon thereafter for roadmap disagreements with the Broadcom leadership.<ref>[http://news.cnet.com/Broadcom-ousts-ServerWorks-chief/2100-1006_3-994245.html Broadcom ousts ServerWorks chief]</ref> In 2003, [[Dell]] announced it would skip PCI-X 2.0 in favor of more rapid adoption of PCI Express solutions.<ref>[http://news.cnet.com/2100-1010-992769.html PCI-X marks the spot for IBM, HP]</ref> As reported by [[PC Magazine]], Intel began to sideline PCI-X in their 2004 roadmap, in favor of PCI Express, arguing that the latter had substantial advantages in terms of system latency and power consumption, more dramatically stated as avoiding "the 1,000-pin apocalypse" for their [[Intel Xeon chipsets#NetBurst-based Xeon chipsets|Tumwater]] chipset.<ref>[https://web.archive.org/web/20160304075654/https://www.pcmag.com/article2/0,2817,909447,00.asp Intel Begins Making Its Case Against PCI-X]</ref>
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