Editing PCI Express (section)

== Architecture <span class="anchor" id="SWITCH"></span> ==
[[File:Example PCI Express Topology.svg|thumb|upright=1.25|Example of the PCI&nbsp;Express topology:<br />white "junction boxes" represent PCI&nbsp;Express device downstream ports. The gray ones represent upstream ports.<ref name="pcie-basics" />{{rp|7}}]]
[[File:RouterBOARD RB14e, top view.jpg|thumb|upright=1.25|PCI Express x1 card containing a PCI Express switch (covered by a small [[heat sink]]), which creates multiple endpoints out of one endpoint and lets multiple devices share it]]

[[File:PCie lanes.jpg|thumb|The PCIe slots on a motherboard are often labeled with the number of PCIe lanes they have. Sometimes what may seem like a large slot may only have a few lanes. For instance, a x16 slot with only 4 PCIe lanes (bottom slot) is quite common.<ref>{{cite web |title=What are PCIe Slots and Their Uses |date=18 May 2021 |url=https://pcguide101.com/motherboard/what-are-pcie-slots/ |publisher=PC Guide 101 |access-date=21 June 2021}}</ref>]]

Conceptually, the PCI Express bus is a high-speed [[serial communication|serial]] replacement of the older PCI/PCI-X bus.<ref name="howstuffworks1" /> One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared [[parallel communications|parallel]] [[Bus (computing)|bus]] architecture, in which the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on point-to-point [[Network topology|topology]], with separate [[serial communication|serial]] links connecting every device to the [[root complex]] (host). Because of its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCI Express bus link supports [[Full-duplexed|full-duplex]] communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.

In terms of bus protocol, PCI Express communication is encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCI Express port (described later). Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors (and thus, new motherboards and new adapter boards); PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express preserves [[backward compatibility]] with PCI; legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the PCI Express standard, though new PCI Express features are inaccessible.

The PCI Express link between two devices can vary in size from one to 16 [[#Lane|lane]]s. In a multi-lane link, the packet data is striped across lanes, and peak data throughput scales with the overall link width. The lane count is automatically negotiated during device initialization and can be restricted by either endpoint. For example, a single-lane PCI Express (x1) card can be inserted into a multi-lane slot (x4, x8, etc.), and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure itself to use fewer lanes, providing a failure tolerance in case bad or unreliable lanes are present. The PCI Express standard defines link widths of x1, x2, x4, x8, and x16. Up to and including PCIe 5.0, x12, and x32 links were defined as well but virtually{{clarification needed|date=January 2025}} never used.<ref name="4TrCr" /> This allows the PCI Express bus to serve both cost-sensitive applications where high throughput is not needed, and performance-critical applications such as 3D graphics, networking ([[10 Gigabit Ethernet]] or multiport [[Gigabit Ethernet]]), and enterprise storage ([[Serial attached SCSI|SAS]] or [[Fibre Channel]]). Slots and connectors are only defined for a subset of these widths, with link widths in between using the next larger physical slot size.

As a point of reference, a PCI-X (133&nbsp;MHz 64-bit) device and a PCI Express&nbsp;1.0 device using four lanes (x4) have roughly the same peak single-direction transfer rate of 1064&nbsp;MB/s. The PCI Express bus has the potential to perform better than the PCI-X bus in cases where multiple devices are transferring data simultaneously, or if communication with the PCI Express peripheral is [[Two-way communication|bidirectional]].

=== Interconnect <span class="anchor" id="LINK"></span> ===
[[File:PCI Express Terminology.svg|thumb|A PCI Express link between two devices consists of one or more lanes, which are [[dual simplex]] channels using two [[differential signaling]] pairs.<ref name="pcie-basics" />{{rp|3}}]]

PCI Express devices communicate via a logical connection called an ''interconnect''<ref name="faq1" /> or ''link''. A link is a point-to-point communication channel between two PCI Express ports allowing both of them to send and receive ordinary PCI requests (configuration, I/O or memory read/write) and [[interrupt]]s ([[Peripheral Component Interconnect#Interrupts|INTx]], [[Message Signaled Interrupts|MSI or MSI-X]]). At the physical level, a link is composed of one or more ''lanes''.<ref name="faq1" /> Low-speed peripherals (such as an [[IEEE 802.11|802.11]] [[Wi-Fi]] [[Wireless network interface card|card]]) use a single-lane (x1) link, while a graphics adapter typically uses a much wider and therefore faster 16-lane (x16) link.

=== Lane <span class="anchor" id="LANE"></span> ===
A lane is composed of two [[differential signaling]] pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or [[signal trace]]s. Conceptually, each lane is used as a [[full-duplex]] [[byte stream]], transporting data packets in eight-bit "byte" format simultaneously in both directions between endpoints of a link.<ref name="2Nt8T" /> Physical PCI Express links may contain 1, 4, 8 or 16 lanes.<ref name="Gchhw" /><ref name="pcie-basics" />{{rp|4,5}}<ref name="faq1" /> Lane counts are written with an "x" prefix (for example, "x8" represents an eight-lane card or slot), with x16 being the largest size in common use.<ref name="odC7t" /> Lane sizes are also referred to via the terms "width" or "by" e.g., an eight-lane slot could be referred to as a "by 8" or as "8 lanes wide."

For mechanical card sizes, see [[#Form factors|below]].

=== Serial bus ===
{{unreferenced section|date=March 2018}}
The bonded serial [[Bus (computing)|bus]] architecture was chosen over the traditional parallel bus because of the inherent limitations of the latter, including [[half-duplex]] operation, excess signal count, and inherently lower [[Bandwidth (computing)|bandwidth]] due to [[timing skew]]. Timing skew results from separate electrical signals within a parallel interface traveling through conductors of different lengths, on potentially different [[printed circuit board]] (PCB) layers, and at possibly different [[Signal velocity|signal velocities]]. Despite being transmitted simultaneously as a single [[Word (data type)|word]], signals on a parallel interface have different travel duration and arrive at their destinations at different times. When the interface clock period is shorter than the largest time difference between signal arrivals, recovery of the transmitted word is no longer possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz.

[[File:PCIe vs PCI.gif|thumb|'''Highly simplified''' topologies of the Legacy PCI Shared (Parallel) Interface and the PCIe Serial Point-to-Point Interface<ref name="P7MD8" />]]

A serial interface does not exhibit timing skew because there is only one differential signal in each direction within each lane, and there is no external clock signal since clocking information is [[Clock recovery|embedded]] within the serial signal itself. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz range. PCI Express is one example of the general trend toward replacing parallel buses with serial interconnects; other examples include [[Serial ATA]] (SATA), [[USB]], [[Serial Attached SCSI]] (SAS), [[FireWire]] (IEEE 1394), and [[RapidIO]]. In digital video, examples in common use are [[Digital Visual Interface|DVI]], [[HDMI]], and [[DisplayPort]].

Multichannel serial design increases flexibility with its ability to allocate fewer lanes for slower devices.