Editing PCI Mezzanine Card (section)

==Variants==
Additional standards exist that define variants of the standard PMC. For example,
* PMC-X ([[PCI-X]] PMC) defined by the [[VMEbus|VITA]] 39 standard
* PPMC (aka PrPMC; processor PMC) is defined by the VITA 32 standard. I.e. for allowing processors to have host or monarch support on a PMC. Additional signaling is defined so that the PrPMC can work as the host processor on a PCI bus. The intention is to allow a monarch PMC to control the PCI bus. This is usually a requirement if the PMC is to act as a host processor module.
* CCPMC (conduction-cooled PMC) defined by the VITA 20 standard
* XMC, or Switched Mezzanine Card (PMC with high-speed serial fabric interconnect) defined by the VITA 42 standard. XMC specifies a fifth connector ("P15") that supports [[PCI Express]] (VITA 42.3) or other high-speed serial formats such as Serial [[RapidIO]] (VITA 42.2) and Parallel [[RapidIO]] (VITA 42.1).
*[[FMC – FPGA Mezzanine Card]] provides a standard mezzanine form factor that offers a flexible, modular I/O interface to an FPGA located on a host system baseboard or carrier card.
* OAI-OAM (Open Accelerator Infrastructure - Accelerator Module) standard from [[Open Compute Project]], describes AI accelerator cards for blade servers, up to 8 cards on a universal base board, each with 7 PCIe x16 links, 12 V or 48 to 60 V power line, up to 600 W TBP (total board power) with air cooling, 600+ W with liquid cooling, interchangeable heatsinks and coldplates.<ref>{{cite web | url=https://www.opencompute.org/projects/open-accelerator-infrastructure | title=Open Compute Project }}</ref>