Editing PDP-10 (section)

==Models and technical evolution==
[[File:KA10 mod end.jpg|thumb|[[Flip Chip (trademark)|Flip Chip]] from a DEC KA10, containing 9 transistors, 1971]]
[[File:DEC-10 Memory Bus Terminator H866 top view.jpg|thumb|Quick Latch Memory Bus Terminator, used on KI10, 1973]]
[[File:KL10-backplane.jpg|thumb|KL10 Wire-Wrap CPU Backplane]]

The original PDP-10 processor is the KA10, introduced in 1968.<ref>{{Cite web|url=http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HMAA-D%20PDP-10%20KA10%20Central%20Processor%20Maintenance%20Manual%20Volume%20I.pdf|title=PDP10 manual|date=Dec 1968}}</ref> It uses discrete [[transistor]]s packaged in DEC's [[Flip Chip (trademark)|Flip-Chip]] technology, with backplanes [[wire wrap]]ped via a semi-automated manufacturing process.  Its [[Magnetic-core memory|cycle time]] is 1&nbsp;μs and its add time 2.1&nbsp;μs.<ref>Digital Equipment Corporation, ''The digital [[Small Computer Handbook|small computer handbook]]'', p. 376</ref> In 1973, the KA10 was replaced by the KI10, which uses [[transistor–transistor logic]] (TTL) [[Integrated circuit#SSI|SSI]]. This was joined in 1975 by the higher-performance KL10 (later faster variants), which is built from [[emitter-coupled logic]] (ECL), [[microprogram]]med, and has [[CPU cache|cache]] memory. The KL10's performance was about 1 megaflops using 36-bit floating point numbers on matrix row reduction. It was slightly faster than the newer [[VAX-11/750]], although more limited in memory.

A smaller, less expensive model, the KS10, was introduced in 1978, using TTL and [[AMD Am2900|Am2901]] [[bit-slice]] components and including the [[PDP-11]] [[Unibus]] to connect peripherals. The KS10 was marketed as the DECSYSTEM-2020, part of the DECSYSTEM-20 range; it was DEC's entry in the [[Distributed computing|distributed processing]] arena, and it was introduced as "the world's lowest cost mainframe computer system."<ref>{{Cite web|url=http://gordonbell.azurewebsites.net/digital/timeline/1978-2.htm|title=DECSYSTEM-2020|website=gordonbell.azurewebsites.net}}</ref>

===KA10===
The KA10 has a maximum main memory capacity (both virtual and physical) of 256 [[kiloword]]s (equivalent to 1152 [[kilobyte]]s); the minimum main memory required is 16 kilowords. As supplied by DEC, it did not include [[paging]] hardware; [[memory management]] consists of two sets of protection and relocation registers, called ''[[base and bounds]]'' registers. This allows each half of a user's [[address space]] to be limited to a set section of [[main memory]], designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and [[read-write]] data/[[Stack (data structure)|stack]] segment (normally the low segment) used by [[TOPS-10]]  and later adopted by [[Unix]]. Some KA10 machines, first at MIT, and later at [[BBN Technologies|Bolt, Beranek and Newman]] (BBN), were modified to add [[virtual memory]]<ref>{{cite web |url=http://bitsavers.org/pdf/bbn/pager/Technical_Details_of_the_BBN_Pager_Model_701_197007.pdf |title=Technical Details of the BBN Pager Model 701 |first1=Theodore R. |last1=Strollo |first2=Jerry D. |last2=Burchflel |first3=Raymond S. |last3=Tomlinson |author3-link=Ray Tomlinson |date=July 22, 1970 |publisher=[[BBN Technologies|Bolt, Beranek and Newman]]}}</ref><ref>{{cite web |title=A Virtual Memory System for the PDP-10 KA10 Processor
|url=https://apps.dtic.mil/sti/citations/ADA028987
|last=McNamee |first=L. P. |date=1976}}</ref> and support for [[demand paging]],<ref>{{cite journal |title=TENEX, a Paged Time Sharing System for the PDP-10
|journal=[[Communications of the ACM]]
|volume=15|issue=3
|url=https://cseweb.ucsd.edu//classes/wi19/cse221-b/papers/bobrow72.pdf
|citeseerx=10.1.1.509.1454
|last1=Bobrow |first1=Daniel G. |author1-link=Daniel Bobrow
|last2=Burchfiel |first2=Jerry D.
|last3=Murphy |first3=Daniel L. |author3-link=Daniel Murphy (computer scientist)
|last4=Tomlinson |first4=Raymond S. |author4-link=Ray Tomlinson
|date=March 1972 
|pages=135–143
|doi=10.1145/361268.361271
|s2cid=52848167
|quote=PDP-10 processor augmented by special paging hardware}}</ref><ref>{{cite web |date=June 1, 1982
|title=DECsystem-10/DECSYSTEM-20 Processor Reference Manual
|url=http://pdp10.nocrew.org/docs/ad-h391a-t1.pdf
|quote=DECsystem-10 ... dynamic paging and working set management}}</ref> and more physical memory.

The KA10 weighs about {{convert|1920|lb|kg}}.<ref>{{cite book |title=PDP-10 Installation Manual |url=http://www.bitsavers.org/pdf/dec/pdp10/KA10/PDP-10_InstallationMan.pdf |page=5 |publisher=Digital Equipment Corporation}}</ref>

The 10/50 was the top-of-the-line Uni-processor KA machine<ref name=JSYS104>{{cite web
|url=http://tenex.opost.com/hbook.html |title=Origins and Development of TOPS-20
|last=Murphy |first=Dan |date=1989}}</ref> at the time when the ''PA1050'' software package was introduced. Two other KA10 models were the uniprocessor 10/40, and the dual-processor 10/55.<ref>{{cite web 
|title=PDP-10 models |date=June 30, 2001 |url=http://www.inwap.com/pdp10/models.txt
|quote=PDP 1055 Dual processor (1050) system ...  early DEC-10 monitors}}</ref>{{efn|also marketed as 1040, 1050, 1055, as per the KI/KL models as 1060, 1070, etc.}}

===KI10===
The KI10 introduced support for paged memory management, and also support a larger physical address space of 4 [[Word (data type)|megawords]]. KI10 models include 1060, 1070 and 1077, the latter incorporating two CPUs.

===KL10===
[[File:PDP-10 1090.jpg|thumb|KL10-DA 1090 [[CPU]] and 6 Memory Modules]]
The original KL10 PDP-10 (also marketed as DECsystem-10) models (1080, 1088, etc.) use the original PDP-10 memory bus, with external memory modules. Module in this context meant a cabinet, dimensions roughly (WxHxD) 30 x 75 x 30 in. with a capacity of 32 to 256 kWords of [[magnetic-core memory]]. The processors used in the [[DECSYSTEM-20]] (2040, 2050, 2060, 2065), commonly but incorrectly called "KL20", use internal memory, mounted in the same cabinet as the [[Central processing unit|CPU]]. The 10xx models also have different packaging; they come in the original tall PDP-10 cabinets, rather than the short ones used later on for the DECSYSTEM-20.  The differences between the 10xx and 20xx models were primarily which operating system they ran, either TOPS-10 or [[TOPS-20]]. Apart from that, differences are more cosmetic than real; some 10xx systems have "20-style" internal memory and I/O, and some 20xx systems have "10-style" external memory and an I/O bus.  In particular, all ARPAnet TOPS-20 systems had an I/O bus because the AN20 [[Interface Message Processor|IMP]] interface was an I/O bus device.  Both could run either TOPS-10 or TOPS-20 microcode and thus the corresponding operating system.

====Model B====
The later Model B version of the 2060 processors removes the 256 [[binary prefix|kilo]][[Word (data type)|word]] limit on the virtual address space by supporting up to 32 "sections" of up to 256 kilowords each, along with substantial changes to the instruction set.  The two versions are effectively different CPUs.  The first operating system that takes advantage of the Model B's capabilities is TOPS-20 release 3, and user mode extended addressing is offered in TOPS-20 release 4.  TOPS-20 versions after release 4.1 only run on a Model B.

TOPS-10 versions 7.02 and 7.03 also use extended addressing when run on a 1090 (or 1091) Model B processor running TOPS-20 microcode.

====MCA25====
The final upgrade to the KL10 was the MCA25 upgrade of a 2060 to 2065 (or a 1091 to 1095), which gave some performance increases for programs which run in multiple sections.

====Massbus====
The I/O architecture of the 20xx series KL machines is based on a DEC bus design called the [[Massbus]]. While many attributed the success of the PDP-11 to DEC's decision to make the PDP-11 Unibus an open architecture, DEC reverted to prior philosophy with the KL, making Massbus both unique and proprietary. Consequently, there were no aftermarket peripheral manufacturers who made devices for the Massbus, and DEC chose to price their own Massbus devices, notably the RP06 disk drive, at a substantial premium above comparable IBM-compatible devices. [[CompuServe]] for one, designed its own alternative disk controller that could operate on the Massbus, but connect to IBM style 3330 disk subsystems.

====Front-end processors====
[[File:KL10-front-end.jpg|thumb|KL10 frontend PDP-11/40]]
The KL class machines have a PDP-11/40 [[front-end processor]] for system start-up and monitoring. The PDP-11 is booted from a dual-ported RP06 disk drive (or alternatively from an 8" [[floppy disk]] drive or [[DECtape]]), and then commands can be given to the PDP-11 to start the main processor, which is typically booted from the same RP06 disk drive as the PDP-11. The PDP-11 performs watchdog functions once the main processor is running.

Communication with IBM mainframes, including [[Remote job entry|Remote Job Entry]] (RJE), was accomplished via a DN61 or DN-64 front-end processor, using a PDP-11/40 or PDP-11/34a.<ref>{{Cite web|url=http://www.inwap.com/pdp10/usenet/decnet|title=USENET alt.sys.pdp10 postings about PDP-10 front end processors}}</ref><ref>{{cite web|url=http://pdp-10.trailing-edge.com/BB-J724A-SM_1980/01/documentation/dn60m.man.html|title=DN60 Maintenance Manual|id=JBS-77-001-02-U|date=October 31, 1978|publisher=Digital Equipment Corporation}}</ref>

===KS10===
[[File:KS10-open.jpg|thumb|KS10]]
The KS10 is a lower-cost PDP-10 built using [[AMD Am2900|AMD 2901]] [[bit-slicing|bit-slice]] chips, with an [[Intel 8080|Intel 8080A]] microprocessor as a control processor.<ref>{{cite book|url=http://www.bitsavers.org/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf|title=KS10-Based DECSYSTEM-2020 Technical Manual|id=EK-0KS10-TM-002|date=September 1979|edition=Second|publisher=Digital Equipment Corporation}}</ref> The KS10 design was crippled to be a Model A even though most of the necessary data paths needed to support the Model B architecture are present.  This was no doubt intended to [[market segmentation|segment the market]], but it greatly shortened the KS10's product life.

The KS system uses a similar boot procedure to the KL10. The 8080 control processor loads the microcode from an RM03, RM80, or RP06 disk or magnetic tape and then starts the main processor. The 8080 switches modes after the operating system boots and controls the console and remote diagnostic serial ports.

===Magnetic tape drives===
Two models of [[tape drive]]s were supported by the TM10 Magnetic Tape Control subsystem:
* TU20 Magnetic Tape Transport – 45 ips (inches/second)
* TU30 Magnetic Tape Transport – 75 ips (inches/second)
* TU45 Magnetic Tape Transport – 75 ips (inches/second)
A mix of up to eight of these could be supported, using [[7-track tape|seven-track]] or [[9-track tape|nine-track]] devices. The TU20 and TU30 each came in A (9-track) and B (7-track) versions, and all of the aforementioned tape drives could read/write from/to 200 [[Bits Per Inch|BPI]], 556 BPI and 800 BPI IBM-compatible tapes.

The TM10 Magtape controller was available in two submodels:
* TM10A did cycle-stealing to/from PDP-10 memory using the KA10 Arithmetic Processor
* TM10B accessed PDP-10 memory using a DF10 Data Channel, without "cycle stealing" from the KA10 Arithmetic Processor<ref name=HW10.KA10>{{cite book
|url=http://bitsavers.trailing-edge.com/pdf/dec/pdp10/KA10/DEC_10-HAAB-D_SitePrep_May70.pdf
|title=PDP-10 Site Preparation Guide 
|publisher=Digital Equipment Corporation |date=May 1970}}</ref>{{rp|49}}