Editing Pentium II (section)

==Overview==
The Pentium II microprocessor was largely based upon the [[microarchitecture]] of its predecessor, the [[Pentium Pro]], but with some significant improvements.<ref>{{cite journal |title=MMX Microarchitecture of Pentium Processors With MMX Technology and Pentium II Microprocessors |journal=Intel Technology Journal |url=https://www.cs.nmsu.edu/~pfeiffer/classes/473/notes/micro.pdf |year=1997|page=5|access-date=September 1, 2017|archive-url=https://web.archive.org/web/20110112073044/http://www.cs.nmsu.edu/~pfeiffer/classes/473/notes/micro.pdf |archive-date=January 12, 2011|url-status=dead}}</ref>

Unlike previous Pentium and Pentium Pro processors, the Pentium II CPU was packaged in a [[Slot 1|slot]]-based module rather than a [[CPU socket]]. The processor and associated components were carried on a [[daughterboard]] similar to a typical expansion board within a plastic cartridge. A fixed or removable [[heatsink]] was carried on one side, sometimes using its own fan.<ref>Pabst, Thomas. [https://archive.today/20120918142840/http://www.tomshardware.com/1998/05/03/intel/ Intel's Slot 1 CPUs Uncovered], Tom's Hardware, May 3, 1998.</ref>

This larger package was a compromise allowing Intel to separate the secondary [[CPU cache|cache]] from the processor while still keeping it on a closely coupled [[back-side bus]]. The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. However, its associativity was increased to 16-way (compared to 4-way on the Pentium Pro) and its size was always 512&nbsp;KB, twice of the smallest option of 256&nbsp;KB on the Pentium Pro. Off-package cache solved the Pentium Pro's low yield issues, allowing Intel to introduce the Pentium II at a mainstream price level.<ref name=TomsPIIKlamath>Pabst, Thomas. [https://web.archive.org/web/20060329130136/http://www.tomshardware.com/1997/03/01/the_intel_pentium_ii_/ The Intel Pentium II ('Klamath') CPU], Tom's Hardware, March 1, 1997.</ref><ref name=AnandP2klamath>Lal Shimpi, Anand. [http://www.anandtech.com/showdoc.aspx?i=125&p=1 Intel Pentium II], Anandtech, May 30, 1997.</ref>

Intel improved [[16-bit]] code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap, by adding segment register caches. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The issues with partial registers was also addressed by adding an internal flag to skip pipeline flushes whenever possible.<ref>{{cite web |url=http://qcd.phys.cmu.edu/QCDcluster/intel/vtune/reference/LipsPro_Partial_Stall.htm|title=Partial Register Stall|website=qcd.phys.cmu.edu |access-date=April 23, 2019|archive-date=January 6, 2018|archive-url=https://web.archive.org/web/20180106083054/http://qcd.phys.cmu.edu/QCDcluster/intel/vtune/reference/LipsPro_Partial_Stall.htm|url-status=dead}}</ref> To compensate for the slower L2 cache, the Pentium II featured 32&nbsp;KB of L1 cache, double that of the Pentium Pro, as well as 4 write buffers (vs. 2 on the Pentium Pro); these can also be used by either pipeline, instead of each one being fixed to one pipeline.<ref name="PIIMANUAL">{{cite web|url=https://ftp.utcluj.ro/pub/docs/publicatii/intel/pentiumII.pdf|title=Pentium II Processor Developer's Manual|year=1997|access-date=September 1, 2017|pages=2–14}}</ref><ref>[http://www.pcguide.com/ref/cpu/fam/g6PII-c.html], PC Guide, accessed July 16, 2016.</ref> The Pentium II was also the first P6-based CPU to implement the [[MMX (instruction set)|Intel MMX]] integer [[SIMD]] instruction set which had already been introduced on the [[Pentium MMX]].<ref name=TomsPIIKlamath />

The Pentium II was a more consumer-oriented version of the Pentium Pro. It was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as [[Windows 9x]], and multimedia applications. The slower and cheaper L2 cache's performance penalty was mitigated by the doubled L1 cache and architectural improvements for legacy code. General processor performance was increased while costs were cut.<ref name=TomsPIIKlamath /><ref>Pabst, Thomas. [https://archive.today/20130204145622/http://www.tomshardware.com/1997/04/30/the_empire_strikes_back/ The Empire Strikes Back: Intel's Pentium II CPU], Tom's Hardware, April 30, 1997.</ref>

All ''Klamath'' and some early ''Deschutes'' Pentium IIs use a combined L2 cache controller / [[tag RAM]] chip that only allows for 512&nbsp;MB to be cached; while more RAM could be installed in theory, this would result in very slow performance. While this limit was practically irrelevant for the average home user at the time, it was a concern for some workstation or server users. Presumably, Intel put this limitation deliberately in place to distinguish the Pentium II from the more upmarket Pentium Pro line, which has a full 4&nbsp;GB cacheable area. The '82459AD' revision of the chip on some 333&nbsp;MHz and all 350&nbsp;MHz and faster Pentium IIs lifted this restriction and also offered a full 4 GB cacheable area.<ref>[http://www.tomshardware.com/reviews/overclocking-special,94-2.html], Tom's Hardware, accessed July 16, 2016.</ref><ref>[http://www.pcguide.com/ref/mbsys/cache/charCacheability-c.html], PC Guide, accessed July 16, 2016.</ref>