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PowerPC 970
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==Design== [[File:PPC-970fx.jpg|thumb|PowerPC 970FX processor]] The PowerPC 970 is a single core derivative of the [[POWER4]] and can process both [[32-bit]] and [[64-bit]] PowerPC [[instruction (computer science)|instruction]]s natively. It has a hardware [[Instruction prefetch|prefetch unit]] and a three way [[Branch predictor|branch prediction unit]]. Like the POWER4, the front-end is nine stages long. The PowerPC 970 can fetch and decode up to eight instructions, dispatch up to five to reserve stations, issue up to eight to the execution units and retire up to five per cycle. The execution pipelines were lengthened compared to the POWER4 to achieve higher [[Instructions per cycle|IPC]]. It has eight execution units: two [[arithmetic logic unit]]s (ALUs), two [[double-precision floating-point format|double-precision]] [[floating-point unit]]s, two load/store units and two [[AltiVec]] units.<ref name="MPR:2002-10-28">Halfhill, Tom R. (October 28, 2002). "IBM Trims Power4, Adds AltiVec". ''[[Microprocessor Report]]''.</ref> One of the AltiVec units executes integer and floating-point instructions, and the other only permute instructions. The latter has three subunits for simple integer, complex integer and floating-point instructions. These units have pipelines of varying lengths: 10 stages for simple integer and permute instructions, 13 stages for complex integer instructions and 16 stage for floating-point instructions.<ref name="MPR:2002-10-28"/> The processor has two unidirectional 32-bit [[double data rate]] (DDR) buses (one for reads, the other for writes) to the system controller chip ([[Northbridge (computing)|northbridge]]) running at one quarter of the processor core speed. The buses also carry addresses and control signals in addition to data so only a percentage of the peak bandwidth can be realized (6.4 GB/s at 450 MHz). As the buses are unidirectional, each direction can realize only half the aggregate bandwidth, or 3.2 GB/s.<ref name="MPR:2002-10-28"/>
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