Open main menu
Home
Random
Recent changes
Special pages
Community portal
Preferences
About Wikipedia
Disclaimers
Incubator escapee wiki
Search
User menu
Talk
Dark mode
Contributions
Create account
Log in
Editing
Programmable logic device
(section)
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
== History == In 1969, [[Motorola]] offered the XC157, a mask-programmed gate array with 12 gates and 30 uncommitted input/output pins.<ref name = "Motorola XC173">{{cite book | title = Motorola Semiconductor Data Book, Fourth Edition | publisher = Motorola Inc. | page = IC-73 | year = 1969 }}</ref> In 1970, [[Texas Instruments]] developed a mask-programmable IC based on the [[IBM]] read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 [[JK flip-flop]]s for memory. TI coined the term ''[[programmable logic array]]'' (PLA) for this device.<ref name = "TI PLA 1970">{{Cite book | last = Andres | first = Kent | title = A Texas Instruments Application Report: MOS programmable logic arrays. | publisher = Texas Instruments | date = October 1970 | id = Bulletin CA-158}} Report introduces the TMS2000 and TMS2200 series of mask programmable PLAs.</ref> In 1971, [[General Electric]] Company (GE) was developing a programmable logic device based on the new [[programmable read-only memory]] (PROM) technology. This experimental device improved on IBM's ROAM by allowing multilevel logic. Intel had just introduced the floating-gate [[UV EPROM]] so the researcher at GE incorporated that technology. The GE device was the first erasable PLD ever developed, predating the [[Altera]] EPLD by over a decade. GE obtained several early patents on programmable logic devices.<ref name = "US Patents 3,818,452">Greer, David L. ''Electrically Programmable Logic Circuits'' [https://patents.google.com/patent/US3818452 US Patent 3,818,452]. Assignee: General Electric, Filed: April 28, 1972, Granted: June 18, 1974</ref><ref name = "US Patents 3,816,725">Greer, David L. ''Multiple Level Associative Logic Circuits'' [https://patents.google.com/patent/US3816725 US Patent 3,816,725]. Assignee: General Electric, Filed: April 28, 1972, Granted: June 11, 1974</ref><ref name = "US Patents 3,849,638">Greer, David L. ''Segmented Associative Logic Circuits'' [https://patents.google.com/patent/US3849638 US Patent 3,849,638]. Assignee: General Electric, Filed: July 18, 1973, Granted: November 19, 1974</ref> In 1973 [[National Semiconductor]] introduced a mask-programmable PLA device (DM7575) with 14 inputs and 8 outputs with no memory registers. This was more popular than the TI part but the cost of making the metal mask limited its use. The device is significant because it was the basis for the field programmable logic array produced by [[Signetics]] in 1975, the 82S100. ([[Intersil]] actually beat Signetics to market but poor yield doomed their part.)<ref name = "Intersil IM5200">{{cite journal | title = Semiconductors and IC's : FPLA | journal = EDN | volume = 20 | issue = 13 | pages = 66 | publisher = Cahners Publishing | location = Boston, MA | date = July 20, 1975 }} Press release on Intersil IM5200 field programmable logic array. Fourteen inputs pins and 48 product terms. Avalanched-induced-migration programming. Unit price was $37.50</ref><ref name = "Signetics 82S100">{{cite journal | title = FPLA's give quick custom logic| journal = EDN | volume = 20 | issue = 13 | pages = 61 | publisher = Cahners Publishing | location = Boston, MA | date = July 20, 1975 }} Press release on Signetics 82S100 and 82S101 field programmable logic arrays. Fourteen inputs pins, 8 output pins and 48 product terms. NiCr fuse link programming.</ref> In 1974 GE entered into an agreement with [[Monolithic Memories]] (MMI) to develop a mask-programmable logic device incorporating the GE innovations. The device was named ''programmable associative logic array'' or PALA. The MMI 5760 was completed in 1976 and could implement multilevel or sequential circuits of over 100 gates. The device was supported by a GE design environment where Boolean equations would be converted to mask patterns for configuring the device. The part was never brought to market.<ref name = "Pellerin 1991">{{Cite book | last = Pellerin | first = David |author2=Michael Holley | title = Practical Design Using Programmable Logic | publisher = Prentice-Hall | year = 1991 | page = 15 | isbn = 0-13-723834-7 }}</ref>
Edit summary
(Briefly describe your changes)
By publishing changes, you agree to the
Terms of Use
, and you irrevocably agree to release your contribution under the
CC BY-SA 4.0 License
and the
GFDL
. You agree that a hyperlink or URL is sufficient attribution under the Creative Commons license.
Cancel
Editing help
(opens in new window)