Editing RapidIO (section)

== History ==
The RapidIO protocol was originally designed by [[Mercury Computer Systems]] and [[Motorola]] ([[Freescale]]) as a replacement for Mercury's RACEway proprietary bus and Freescale's PowerPC bus.<ref>{{cite book |last=Fuller |first=Sam |date=27 December 2004 |title=RapidIO: The Embedded System Interconnect |publisher=John Wiley & Sons Ltd |chapter=Preface |isbn=0-470-09291-2 }}</ref> The RapidIO Trade Association was formed in February 2000, and included telecommunications and storage OEMs as well as FPGA, processor, and switch companies.

=== Releases ===

The RapidIO specification revision 1.1 (3xN Gen1), released in March 2001, defined a wide, parallel bus. This specification did not achieve extensive commercial adoption.

The RapidIO specification revision 1.2, released in June 2002,<ref>{{cite web |url=http://www.rapidio.org/rapidio-specifications/#tab1752 |title=RapidIO Standard Revision 1.2 |author=<!--Staff writer(s); no by-line.--> |date=26 June 2002 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=9 October 2014 |archive-date=24 December 2016 |archive-url=https://web.archive.org/web/20161224232948/http://www.rapidio.org/rapidio-specifications/#tab1752 |url-status=dead }}</ref> defined a serial interconnection based on the XAUI physical layer. Devices based on this specification achieved significant commercial success within wireless baseband,<ref>{{cite web |url=http://files.shareholder.com/downloads/IDTI/3533679921x0x500036/14BEEAA3-863E-41DD-9CB2-4F99279AC6EA/IDT_2011Annual_compositetotal.pdf |title=Integrated Device Technology 2011 Annual Report |author=<!--Staff writer(s); no by-line.--> |date=6 June 2011 |page=4 |website=www.idt.com |publisher=Integrated Device Technology Inc |access-date=9 October 2014 |archive-date=3 March 2016 |archive-url=https://web.archive.org/web/20160303213710/http://files.shareholder.com/downloads/IDTI/3533679921x0x500036/14BEEAA3-863E-41DD-9CB2-4F99279AC6EA/IDT_2011Annual_compositetotal.pdf |url-status=dead }}</ref> imaging and military computing.<ref>{{cite web |url=http://www.linleygroup.com/newsletters/newsletter_detail.php?num=5064 |title= RapidIO Reaches for the Clouds |author=Jag Bolaria |date=October 15, 2013 |website=www.linleygroup.com |publisher=The Linley Group |access-date=9 October 2014}}</ref>

The RapidIO specification revision 1.3 was released in June 2005.

The RapidIO specification revision 2.0 (6xN Gen2), was released in March 2008.<ref>{{cite web |url=http://www.rapidio.org/files/Rev2.0_stack2.zip |title=RapidIO Standard Revision 2.0 |author=<!--Staff writer(s); no by-line.--> |date=23 February 2005 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=9 October 2014 |archive-date=2 December 2016 |archive-url=https://web.archive.org/web/20161202223414/http://www.rapidio.org/files/Rev2.0_stack2.zip |url-status=dead }}</ref> This added more port widths (2×, 8×, and 16×) and increased the maximum lane speed to 6.25&nbsp;[[Baud|GBd]] / 5&nbsp;Gbit/s.

The RapidIO specification revision 2.1 was released in September 2009.

The RapidIO specification revision 2.2 was released in May 2011.

The RapidIO specification revision 3.0 (10xN Gen3) released in October 2013.<ref>{{cite web |url=http://www.rapidio.org/rapidio-specifications/#tab1930 |title=RapidIO Standard Revision 3.0 |author=<!--Staff writer(s); no by-line.--> |date=10 November 2013 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=9 October 2014 |archive-date=24 December 2016 |archive-url=https://web.archive.org/web/20161224232948/http://www.rapidio.org/rapidio-specifications/#tab1930 |url-status=dead }}</ref> The following changes were made:
* Based on industry-standard Ethernet 10GBASE-KR electrical specifications for short (20&nbsp;cm + connector) and long (1&nbsp;m + 2 connector) reach applications
* Directly leverages the Ethernet 10GBASE-KR DME training scheme for long-reach signal quality optimization
* Defines a 64b/67b encoding scheme (similar to the [[Interlaken (networking)|Interlaken]] standard) to support both [[Copper wire and cable|copper]] and [[Optical fiber cable|optical]] interconnects and to improve [[spectral efficiency|bandwidth efficiency]]
* Dynamic asymmetric links to save power (for example, 4× in one direction, 1× in the other)
* Addition of a time synchronization capability similar to [[Precision Time Protocol|IEEE 1588]], but much less expensive to implement
* Support for 32-bit device IDs, increasing maximum system size and enabling innovative hardware virtualization support
* Revised routing table programming model simplifies network management software
* Packet exchange protocol optimizations

The RapidIO specification revision 3.1, was released in October 2014.<ref>{{cite web |url=http://www.rapidio.org/wp-content/uploads/2014/10/RapidIO-3.1-Specification.pdf |title=RapidIO Standard Revision 3.1 |author=<!--Staff writer(s); no by-line.--> |date=13 October 2014 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=18 October 2014 |archive-date=23 October 2014 |archive-url=https://web.archive.org/web/20141023025959/http://www.rapidio.org/wp-content/uploads/2014/10/RapidIO-3.1-Specification.pdf |url-status=dead }}</ref> It  was developed through a collaboration between the RapidIO Trade Association and NGSIS.  Revision 3.1 has the following changes compared to the 3.0 specification:
* MECS Time Synchronization protocol for smaller embedded systems.  MECS Time Synchronization supports redundant time sources.  This protocol is lower cost than the Timestamp Synchronization Protocol introduced in revision 3.0
* [[Pseudorandom binary sequence|PRBS]] test facilities and standard register interface.
* Structurally Asymmetric Link behavioral definition and standard register interface.  These structurally Asymmetric Links carry much more data in one direction than the other, for applications such as sensors or processing pipelines.  Unlike dynamic asymmetric links, Structurally Asymmetric Links allow implementers to remove lanes on boards and in silicon, saving size, weight, and power.  Structurally asymmetric links also allow the use of alternative lanes in the case of a hardware failure on a multi-lane port.
* Extended error log to capture a series of errors for diagnostic purposes
* Space device profiles for endpoints and switches, which define what it means to be a space-compliant RapidIO device.

The RapidIO specification revision 3.2 was released in February 2016.

The RapidIO specification revision 4.0 (25xN Gen4) was released in June 2016.<ref name="auto">{{cite web |url=http://www.rapidio.org/rapidio-specifications/#tab1277 |title=RapidIO Standard Revision 4.0 |author=<!--Staff writer(s); no by-line.--> |date=June 2016 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=15 August 2016 |archive-date=24 December 2016 |archive-url=https://web.archive.org/web/20161224232948/http://www.rapidio.org/rapidio-specifications/#tab1277 |url-status=dead }}</ref> It had the following changes compared to the 3.x specifications:
* Support 25 Gbaud lane rate and physical layer specification, with associated programming model changes
* Allow IDLE3 to be used with any Baud Rate Class, with specified IDLE sequence negotiation
* Increased maximum packet size to 284 bytes in anticipation of Cache Coherency specification
* Support 16 physical layer priorities
* Support “Error Free Transmission” for high throughput isochronous information transfer

The RapidIO specification revision 4.1 was released in July 2017.<ref>{{cite web |url=https://www.vita.com/rapidio-specifications |title=RapidIO Standard Revision 4.1 |date=July 2017 |website=vita.com |publisher=RapidIO Trade Association |access-date=11 August 2019}}</ref>

=== Wireless infrastructure ===
RapidIO fabrics are used in cellular infrastructure 3G, 4G and LTE networks with millions of RapidIO ports shipped<ref>{{cite web|url=http://www.rcrwireless.com/20121203/opinion/reader-forum-cloud-radio-access-small-cell-networks-based-rapidio|title=Reader Forum: Cloud radio access and small cell networks based on RapidIO|website=www.rcrwireless.com|date=3 December 2012 }}</ref> into wireless base stations worldwide. RapidIO fabrics were originally designed to support connecting different types of processors from different manufacturers together in a single system. This flexibility has driven the widespread use of RapidIO in wireless infrastructure equipment where there is a need to combine heterogeneous, DSP, FPGA and communication processors together in a tightly coupled system with low latency and high reliability.

=== Data centers ===
Data center and HPC analytics systems have been deployed using a RapidIO 2D Torus Mesh Fabric,<ref>{{cite web|url=http://www.hpcwire.com/2014/09/24/paypal-finds-order-chaos-hpc/|title=PayPal Finds Order from Chaos with HPC|date=24 September 2014|website=hpcwire.com}}</ref> that provides a high speed general purpose interface among the system cartridges. This allows for applications that benefit from high bandwidth to low latency node-to-node communication.  The RapidIO 2D Torus unified fabric is routed as a torus ring configuration connecting up to 45 server cartridges. Hence, capable of providing 5Gbs per lane connections in each direction to its north, south, east and west neighbors. This allows the system to meet many unique HPC applications where efficient localized traffic is needed.

Also, using an open modular data center and compute platform,<ref>{{cite web|url=http://prodrive-technologies.com/prodrive-technologies-announces-datacenter-hpc-system-dccp-280-rapidio-10-gigabit-ethernet/|title=Prodrive Technologies announces its Datacenter - HPC system (DCCP-280) with RapidIO and 10 Gigabit Ethernet - Prodrive Technologies|date=30 January 2014|website=prodrive-technologies.com}}</ref> a heterogeneous HPC system has showcased the low latency attribute of RapidIO to enable real-time analytics.<ref>{{cite press release|url=http://www.businesswire.com/news/home/20141118005342/en/IDT-Orange-Silicon-Valley-NVIDIA-Accelerate-Computing#.VQqdHuF0Uso|title=IDT, Orange Silicon Valley, NVIDIA Accelerate Computing Breakthrough With RapidIO-based Clusters Ideal for Gaming, Analytics|website=businesswire.com|date=18 November 2014 }}</ref> In March 2015 a top-of-rack switch was announced to drive RapidIO into mainstream data center applications.<ref>{{cite web|url=http://prodrive-technologies.com/prodrive-technologies-launches-prsb-760g2-large-rapidio-networks/|title=Prodrive Technologies Launches PRSB-760G2 for large RapidIO networks - Prodrive Technologies|date=2 March 2015|website=prodrive-technologies.com}}</ref>

=== Aerospace ===
The interconnect or "bus" is one of the critical technologies in the design and development of spacecraft avionic systems that dictate its architecture and level of complexity.  There are a host of existing architectures that are still in use given their level of maturity.  These existing systems are sufficient for a given type of architecture need and requirement.  Unfortunately, for next generation missions a more capable avionics architecture is desired; which is well beyond the capabilities levied by existing architectures.  A viable option for the design and development of these next generation architectures is to leverage existing commercial protocols capable of accommodating high levels of data transfer.

In 2012, RapidIO was selected by the Next Generation Spacecraft Interconnect Standard (NGSIS) working group to serve as the foundation for standard communication interconnects to be used in spacecraft. The NGSIS is an umbrella standards effort that includes RapidIO Version 3.1 development, and a box level hardware standards effort under [[VMEbus International Trade Association|VITA]] 78 called SpaceVPX or High ReliabilityVPX. The NGSIS requirements committee developed extensive requirements criteria with 47 different elements for the NGSIS interconnect. Independent trade study results by NGSIS member companies demonstrated the superiority of RapidIO over other existing commercial protocols, such as InfiniBand, Fibre Channel, and 10G Ethernet. As a result, the group decided that RapidIO offered the best overall interconnect for the needs of next-generation spacecraft.<ref>{{cite web |url=http://www.responsivespace.com/Papers/RS2013/Sessions/SESSION%20I/1005_Collier/1005P.pdf |title= Next Generation Space Interconnect Standard (NGSIS): A Modular Open Standards Approach for High Performance Interconnects for Space |author=Patrick Collier |date=14 October 2013 |page=5  |publisher=Reinventing Space Conference |access-date=9 October 2014}}</ref>

=== PHY roadmap ===
The RapidIO roadmap aligns with Ethernet PHY development. RapidIO specifications for 50&nbsp;GBd and higher links are under investigation.<ref>{{cite web |url=http://www.rapidio.org/rapidio-roadmap/ |title= RapidIO Roadmap |author=<!--Staff writer(s); no by-line.--> |date=10 June 2012 |page=4 |website=www.rapidio.com |publisher=RapidIO Trade Association |access-date=9 October 2014}}</ref>