Editing Resistor–transistor logic (section)

== Implementation ==

=== RTL inverter ===

A bipolar [[Transistor#Transistor as a switch|transistor switch]] is the simplest RTL gate ([[Inverter (logic gate)|inverter]] or NOT gate) implementing [[logical negation]].<ref>[http://www.play-hookey.com/digital_electronics/rtl_gates.html Resistor-Transistor Logic] {{Webarchive|url=https://web.archive.org/web/20181002181106/http://www.play-hookey.com/digital_electronics/rtl_gates.html |date=2018-10-02 }} explains the basic RTL gates and gives some useful calculations</ref> It consists of a [[Common emitter|common-emitter stage]] with a base resistor connected between the base and the input voltage source. The role of the base resistor is to expand the very small transistor input voltage range (about 0.7 V) to the logical "1" level (about 3.5 V) by converting the input voltage into current. Its resistance is settled by a compromise: it is chosen low enough to saturate the transistor and high enough to obtain high input resistance. The role of the collector resistor is to convert the collector current into voltage; its resistance is chosen high enough to saturate the transistor and low enough to obtain low output resistance (high [[fan-out]]).

=== One-transistor RTL NOR gate ===
[[File:RTL NPN NOR Gate.svg|right|thumb|200px|Schematic of a one-transistor RTL NOR gate.]]

With two or more base resistors (R<sub>3</sub> and R<sub>4</sub>) instead of one, the inverter becomes a two-input RTL [[NOR gate]] (see the figure on the right). The logical operation [[Logical disjunction|OR]] is performed by applying consecutively the two arithmetic operations [[addition]] and [[Comparison (mathematics)|comparison]] (the input resistor network acts as a parallel ''voltage summer'' with equally weighted inputs and the following common-emitter transistor stage as a ''voltage comparator'' with a threshold about 0.7 V). The equivalent resistance of all the resistors connected to logical "1" and the equivalent resistance of all the resistors connected to logical "0" form the two legs of a composed voltage divider driving the transistor. The base resistances and the number of the inputs are chosen (limited) so that only one logical "1" is sufficient to create base-emitter voltage exceeding the threshold and, as a result, saturating the transistor. If all the input voltages are low (logical "0"), the transistor is cut-off. The [[pull-down resistor]] R<sub>1</sub> biases the transistor to the appropriate on-off threshold.  The output is inverted since the collector-emitter voltage of transistor Q<sub>1</sub> is taken as output, and is high when the inputs are low. Thus, the analog resistive network and the analog transistor stage perform the logic function NOR.<ref>{{cite book |author=IBM |id=Form 223-6889|year=1960 |title=Transistor Component Circuits |publisher=IBM |url=http://ibm-1401.info/Form223-6889-TransistorComponentCircuits.pdf |series=Customer Engineering Manual of Instruction |accessdate=2010-01-04 |quote=The logical function is performed by the input resistor network and the invert function is accomplished by the common emitter transistor configuration... }}</ref>

=== Multi-transistor RTL NOR gate ===
[[File:RTL 3-Input NOR Gate.svg|right|thumb|300px|Schematic of a multi-transistor RTL NOR gate, as used in the [[Apollo Guidance Computer]] integrated circuits.<ref name=AGC2005011>[[Apollo Guidance Computer]] schematics, [http://klabs.org/history/ech/agc_schematics/logic/5011-1.jpg Dwg. No. 2005011].</ref>]]
[[File:Agc nor2.jpg|right|thumb|300px|Photograph of the dual 3-input NOR gate chip used to build the [[Apollo Guidance Computer]]. Connections (clockwise from top center) ground, inputs (3), output, power (V<sub>cc</sub>), output, inputs (3). The six transistors (two groups of three) are in the center. The thin wires from the terminals to the transistors are resistors. ]]
[[File:Agc flatp.jpg|thumb|right|[[Flatpack (electronics)|Flatpack]] RTL NOR gate integrated circuits in the [[Apollo guidance computer]] ]]

The limitations of the one-transistor RTL NOR gate are overcome by the multi-transistor RTL implementation. It consists of a set of parallel-connected transistor switches driven by the logic inputs (see the figure on the right). In this configuration, the inputs are completely separated and the number of inputs is limited only by the small leakage current of the cut-off transistors at output logical "1". The same idea was used later for building [[Direct-coupled transistor logic|DCTL]], [[Emitter-coupled logic|ECL]], some [[Transistor-transistor logic|TTL]] (7450, 7460), [[NMOS logic|NMOS]] and [[CMOS]] gates.

=== Transistor bias ===
{{Main|Bipolar transistor biasing}}
To ensure stability and predictable output of the bipolar transistors their base-inputs (V<sub>b</sub> or base-terminal voltage) is biased.