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Scalable Coherent Interface
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==History== Soon after the [[FASTBUS|Fastbus]] (IEEE 960) follow-on [[Futurebus]] (IEEE 896) project in 1987, some engineers predicted it would already be too slow for the [[high performance computing]] marketplace by the time it would be released in the early 1990s. In response, a "Superbus" study group was formed in November 1987. Another working group of the [[IEEE Standards Association|standards association]] of the [[Institute of Electrical and Electronics Engineers]] (IEEE) spun off to form a standard targeted at this market in July 1988.<ref>{{Cite web |title= The Scalable Coherent Interface and Related Standards Projects |author= David B. Gustavson |publisher= [[Stanford Linear Accelerator Center]] |date= September 1991 |work= SLAC Publication 5656 |url= http://www.slac.stanford.edu/cgi-wrap/getdoc/slac-pub-5656.pdf |access-date= August 31, 2013 }}</ref> It was essentially a subset of Futurebus features that could be easily implemented at high speed, along with minor additions to make it easier to connect to other systems, such as [[VMEbus]]. Most of the developers had their background from high-speed [[bus (computing)|computer buses]]. Representatives from companies in the computer industry and research community included Amdahl, Apple Computer, [[BBN Technologies|BB&N]], [[Hewlett-Packard]], CERN, Dolphin Server Technology, [[Cray Research]], Sequent, AT&T, Digital Equipment Corporation, McDonnell Douglas, National Semiconductor, Stanford Linear Accelerator Center, Tektronix, Texas Instruments, Unisys, University of Oslo, [[University of Wisconsin]]. The original intent was a single standard for all buses in the computer.<ref name="site">{{Cite web |title= Scalable Coherent Interface and Serial Express Users, Developers, and Manufacturers Association |work= Group web site |url= http://www.scizzl.com/ |access-date= August 31, 2013 }}</ref> The working group soon came up with the idea of using point-to-point communication in the form of insertion rings. This avoided the lumped capacitance, limited physical length/speed of light problems and stub reflections in addition to allowing parallel transactions. The use of insertion rings is credited to Manolis Katevenis who suggested it at one of the early meetings of the working group. The working group for developing the standard was led by David B. Gustavson (chair) and David V. James (Vice Chair).<ref>{{Cite web |title= 1596 WG - Working Group for Scalable Coherent Interface |work= Working group web site |url= http://standards.ieee.org/develop/wg/1596_WG.html |archive-url= https://web.archive.org/web/20160304202506/http://standards.ieee.org/develop/wg/1596_WG.html |url-status= dead |archive-date= March 4, 2016 |access-date= August 31, 2013 }}</ref> David V. James was a major contributor for writing the specifications including the executable C-code.{{Citation needed|date=November 2011}} Stein Gjessing’s group at the University of Oslo used formal methods to verify the coherence protocol and Dolphin Server Technology implemented a node controller chip including the cache coherence logic. [[File:NUMA.svg|thumb|upright=1.2 |Block diagram of one example]] Different versions and derivatives of SCI were implemented by companies like [[Dolphin Interconnect Solutions]], Convex, [[Data General AViiON]] (using cache controller and link controller chips from Dolphin), Sequent and Cray Research. Dolphin Interconnect Solutions implemented a PCI and PCI-Express connected derivative of SCI that provides non-coherent shared memory access. This implementation was used by [[Sun Microsystems]] for its high-end clusters, [[Thales Group]] and several others including volume applications for message passing within HPC clustering and medical imaging. SCI was often used to implement [[non-uniform memory access]] architectures. It was also used by [[Sequent Computer Systems]] as the processor memory bus in their NUMA-Q systems. Numascale developed a derivative to connect with [[HyperTransport#Multiprocessor interconnect|coherent HyperTransport]].
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