Editing Semiconductor device fabrication (section)

==Feature size==
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Feature size is determined by the width of the smallest lines that can be patterned in a semiconductor fabrication process, this measurement is known as the linewidth.<ref>{{cite book | url=https://books.google.com/books?id=PsVVKz_hjBgC&dq=feature+size+semiconductor&pg=SA21-PA48 | title=Handbook of Semiconductor Manufacturing Technology | isbn=978-1-4200-1766-3 | last1=Nishi | first1=Yoshio | last2=Doering | first2=Robert | date=19 December 2017 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=nHm4e7rFNfgC&dq=feature+size+semiconductor&pg=PA8 | title=Fundamental Principles of Optical Lithography: The Science of Microfabrication | isbn=978-0-470-72386-9 | last1=Mack | first1=Chris | date=11 March 2008 | publisher=John Wiley & Sons }}</ref> Patterning often refers to photolithography which allows a device design or pattern to be defined on the device during fabrication.<ref>{{cite book | url=https://books.google.com/books?id=NEkPEAAAQBAJ&dq=photolithography+patterning&pg=PA121 | title=Extending Moore's Law through Advanced Semiconductor Design and Processing Techniques | isbn=978-1-351-24866-2 | last1=Lambrechts | first1=Wynand | last2=Sinha | first2=Saurabh | last3=Abdallah | first3=Jassem Ahmed | last4=Prinsloo | first4=Jaco | date=13 September 2018 | publisher=CRC Press }}</ref> F<sup>2</sup> is used as a measurement of area for different parts of a semiconductor device, based on the feature size of a semiconductor manufacturing process. Many semiconductor devices are designed in sections called cells, and each cell represents a small part of the device such as a memory cell to store data. Thus F<sup>2</sup> is used to measure the area taken up by these cells or sections.<ref>{{cite book | url=https://books.google.com/books?id=FPBjEAAAQBAJ&dq=f2+cell+size&pg=PP22 | title=Semiconductor Memory Devices and Circuits | isbn=978-1-000-56761-8 | last1=Yu | first1=Shimeng | date=19 April 2022 | publisher=CRC Press }}</ref>

A specific '''semiconductor process''' has specific rules on the minimum size (width or CD/Critical Dimension) and spacing for features on each layer of the chip.<ref name="shirriff_die_shrink" />
Normally a new semiconductor process has smaller minimum sizes and tighter spacing.  In some cases, this allows a simple [[die shrink]] of a currently produced chip design to reduce costs, improve performance,<ref name="shirriff_die_shrink">{{cite web|first=Ken|last=Shirriff|url=https://www.righto.com/2020/06/die-shrink-how-intel-scaled-down-8086.html|title=Die shrink: How Intel scaled-down the 8086 processor|date=June 2020|access-date=22 May 2022}}</ref> and increase transistor density (number of transistors per unit area) without the expense of a new design.

Early semiconductor processes had arbitrary names for generations (viz., [[HMOS]] I/II/III/IV and [[CHMOS]] III/III-E/IV/V). Later each new generation process became known as a '''technology node'''<ref>{{cite web|url=https://www.semiconductors.org/wp-content/uploads/2018/08/2003Overall-Roadmap-Technology-Characteristics.pdf|title=Overall Roadmap Technology Characteristics|publisher=[[Semiconductor Industry Association]]}}</ref> or '''process node''',<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|first=Priyank|last=Shukla|website=Design And Reuse}}</ref><ref>{{Cite web|url=https://en.wikichip.org/wiki/technology_node#:~:text=The%20technology%20node%20(also%20process,process%20and%20its%20design%20rules.&text=Generally%2C%20the%20smaller%20the%20technology,faster%20and%20more%20power-efficient.|title=Technology Node - WikiChip|access-date=2020-10-20|archive-date=2020-11-12|archive-url=https://web.archive.org/web/20201112024930/https://en.wikichip.org/wiki/technology_node#:~:text=The%20technology%20node%20(also%20process,process%20and%20its%20design%20rules.&text=Generally%2C%20the%20smaller%20the%20technology,faster%20and%20more%20power-efficient.|url-status=live}}</ref> designated by the process' '''minimum feature size''' in [[nanometers]] (or historically [[Micrometre|micrometers]]) of the process's [[Gate (transistor)|transistor gate]] length, such as the "[[90 nm process]]". However, this has not been the case since 1994,<ref name="Moore">{{Cite web|url=https://spectrum.ieee.org/a-better-way-to-measure-progress-in-semiconductors|title=A Better Way To Measure Progress in Semiconductors|first=Samuel K.|last=Moore|website=IEEE Spectrum: Technology, Engineering, and Science News|date=21 July 2020|access-date=22 May 2022}}</ref> and the number of nanometers used to name process nodes (see the [[International Technology Roadmap for Semiconductors]]) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per unit area).<ref name="ridley" >{{Cite web|url=https://www.pcgamer.com/chipmaking-process-node-naming-lmc-paper/|title=Intel 10nm isn't bigger than AMD 7nm, you're just measuring wrong|first=Jacob|last=Ridley|website=PC Gamer|date=April 29, 2020|access-date=October 21, 2020|archive-date=October 28, 2020|archive-url=https://web.archive.org/web/20201028014834/https://www.pcgamer.com/chipmaking-process-node-naming-lmc-paper/|url-status=live}}</ref>

Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350&nbsp;nm node); however this trend reversed in 2009.<ref name="Moore"/> Feature sizes can have no connection to the nanometers (nm) used in marketing.
For example, Intel's former [[10 nm process]]  actually has features (the tips of [[FinFET]] fins) with a width of 7&nbsp;nm, so the Intel 10&nbsp;nm process is similar in transistor density to [[TSMC]]'s [[7 nm process]]. As another example, GlobalFoundries' 12 and 14&nbsp;nm processes have similar feature sizes.<ref>{{Cite web|url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3|title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review|first=Ian|last=Cutress|website=[[AnandTech]]|access-date=2020-11-07|archive-date=2020-11-12|archive-url=https://web.archive.org/web/20201112015437/https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3|url-status=live}}</ref><ref>{{Cite web|url = https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leading-performance-12lp/|title = VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP|date = 22 July 2018|access-date = 20 October 2020|archive-date = 7 April 2019|archive-url = https://web.archive.org/web/20190407104112/https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leading-performance-12lp/|url-status = live}}</ref><ref name="ridley" />