Editing Silicon on insulator (section)

==Industry need==
SOI technology is one of several manufacturing strategies to allow the continued miniaturization of [[microelectronic]] devices, colloquially referred to as "extending [[Moore's Law]]" (or "More Moore", abbreviated "MM"). Reported benefits of SOI relative to conventional silicon ([[bulk CMOS]]) processing include:<ref>
{{cite web |first=Horacio  |last=Mendez |title=Silicon-on-insulator — SOI technology and ecosystem — Emerging SOI applications |date=April 2009 |publisher=SOI Industry Consortium |url=http://www.soiconsortium.org/pdf/Consortium_9april09_final.pdf }}</ref>
*Lower parasitic capacitance due to isolation from the [[bulk silicon]], which improves power consumption at matched performance
*Resistance to [[latchup]] due to complete isolation of the n- and p-well structures
*Higher performance at equivalent [[IC power-supply pin|VDD]]. Can work at low VDDs<ref>{{cite web |first=Narayan M. |last=Kodeti |title=Silicon On Insulator (SOI) Implementation |date=October 2010 |work=White Paper |publisher=Infotech |url=http://www.infotech-enterprises.com/fileadmin/infotech-enterprises.com/assets/downloads/White_Papers/Infotech_SOI_Paper_Oct_2010.pdf|archive-url=https://web.archive.org/web/20130418043957/http://www.infotech-enterprises.com/fileadmin/infotech-enterprises.com/assets/downloads/White_Papers/Infotech_SOI_Paper_Oct_2010.pdf |archive-date=2013-04-18 }}</ref>
*Reduced temperature dependency due to no doping
*Better yield due to high density, better wafer utilization
*Reduced antenna issues
*No body or well taps are needed
*Lower leakage currents due to isolation thus higher power efficiency
*Inherently [[radiation hardening#Physical|radiation hardened]] (resistant to soft errors), reducing the need for redundancy

From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel [[metrology]] requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder.
The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10&ndash;15% increase to total manufacturing costs.<ref>{{cite web|url=https://www.cnet.com/news/ibm-touts-chipmaking-technology/|title=IBM touts chipmaking technology|date=29 March 2001|website=cnet.com|access-date=22 April 2018}}</ref>{{additional citation needed|date=June 2018}} FD-SOI (Fully Depleted Silicon On Insulator) has been seen as a potential low cost alternative to FinFETs.<ref>{{cite web | url=https://www.eetimes.com/samsung-gf-ramp-fd-soi/ | title=Samsung, GF Ramp FD-SOI | date=27 April 2018 }}</ref>