Editing Source-synchronous (section)

== Reasons for usage ==

A reason that source-synchronous clocking is useful is that it has been observed that all of the circuits within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation.  This means signal propagation delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT. This advantage allows higher speed operation as compared to the traditional technique of providing the clock from a third device to both the transmitter and the receiver.  Another benefit is that higher complexity data-recovery or clock-data-recovery circuits (such as [[Phase-locked loop|PLL]]s) are not required when this technique is used.

Or rather than higher clock speeds, large systems that take advantage of source-synchronous clocking can have the benefit of a higher tolerance of PVT variation of its individual components.

=== Timing Analysis ===

[[Synchronous logic]] elements such as flip-flops have static timing criteria that must be satisfied in order for them to work correctly. In a system-synchronous clock topology where a skew-aligned clock is fed to all devices, the criteria are

<math>T_{clock} > T_{setup} + T_{ko} + T_{skew}</math>

A source-synchronous clock topology eliminates two of these factors, <math>T_{ko}</math> and <math>T_{skew}</math>. The former is eliminated since both clock and data signals are driven by identical flip-flops on the same silicon at the same temperature and voltage, thereby equalizing the <math>T_{ko}</math> seen by both clock and data. The latter is eliminated for the same reason - since the clock and data are driven by identical devices and (ideally) connected with wires of equal length, the skew between clock and data is greatly reduced. For this reason, <math>T_{clock}</math> can be reduced significantly. Since frequency is inversely proportional to clock period, the clock frequency increases as a result.