Editing Southbridge (computing) (section)

==Current status==
Due to the push for [[System on a chip|system-on-chip]] (SoC) processors, modern devices increasingly have the northbridge integrated into the CPU [[Die (integrated circuit)|die]] itself;{{Explain|reason=What push for SoC processors? Explain the context.|date=October 2018}} examples are [[Intel]]'s [[Sandy Bridge]]<ref>{{cite web|last =Vatto|first =Kristian|title=Why Ivy Bridge is still Quad-core?|url= http://www.anandtech.com/show/5174/why-ivy-bridge-is-still-quad-core | website = Anandtech |access-date= September 27, 2015}}</ref> and [[AMD]]'s [[AMD Fusion|Fusion]] processors,<ref>{{cite web|last =Stokes|first = Jon |title= With Fusion, AMD's devils are in the details|url= https://arstechnica.com/business/2010/11/with-fusion-amds-devils-are-in-the-details/ | website =Arstechnica|date = 11 November 2010 |access-date=September 27, 2015}}</ref> both released in 2011. 

With the [[Intel 5 Series]] chipset in 2008, the southbridge became redundant and was replaced by the [[Platform Controller Hub]] (PCH) architecture introduced. AMD did the same with the release of their first APUs in 2011, naming the PCH the [[fusion controller hub]] (FCH), which was only used on AMD's APUs until 2017 when it began to be used on AMD's Zen architecture while dropping the FCH name. 

On Intel platforms, all southbridge features and remaining I/O functions are managed by the PCH, which is directly connected to the CPU via the [[Direct Media Interface]] (DMI).<ref>{{cite web|url= http://www.intel.com/content/www/us/en/chipsets/mainstream-chipsets/mobile-chipset-hm57.html |title=Mobile Intel HM57 Express Chipset |publisher=Intel | access-date= 2014-04-21}}</ref> Intel low-power processors (Haswell-U and onward) and ultra low-power processors (Haswell-Y and onward) also integrate an on-package PCH. Based on its [[Chiplet]] design, [[AMD Ryzen]] processors also integrated some southbridge functions, such as some [[USB]] and [[SATA]]/[[NVMe]] interfaces.<ref>{{Cite web|last=Hagedoorn|first=Hilbert|title=AMD Ryzen 3000: New Block diagram about PCIe 4.0 on Matisse and X570 chipset|url=https://www.guru3d.com/news-story/amd-ryzen-3000-new-block-diagram-about-pcie-4-on-matisse-and-x570-chipset.html|access-date=2020-06-12|website=Guru3D.com|date=23 May 2019 |language=en-us}}</ref>