Editing Speedup (section)

==Definitions==
Speedup can be defined for two different types of quantities: ''[[Latency (engineering)|latency]]'' and ''[[throughput]]''.<ref>{{cite web
| last = Martin
| first = Milo
| title = Performance and Benchmarking
| url=http://www.cis.upenn.edu/~milom/cis501-Fall12/lectures/04_performance.pdf
| access-date = 5 June 2014
}}</ref>

''Latency'' of an architecture is the reciprocal of the execution speed of a task:
: <math>L = \frac{1}{v} = \frac{T}{W},</math>
where
* ''v'' is the execution speed of the task;
* ''T'' is the execution time of the task;
* ''W'' is the execution workload of the task.
''Throughput'' of an architecture is the execution rate of a task:
: <math>Q = \rho vA = \frac{\rho AW}{T} = \frac{\rho A}{L},</math>
where
* ''ρ'' is the execution density (e.g., the number of stages in an [[instruction pipeline]] for a [[pipeline (computing)|pipeline]]d architecture);
* ''A'' is the execution capacity (e.g., the number of [[Central processing unit|processors]] for a parallel architecture).
Latency is often measured in seconds per unit of execution workload. Throughput is often measured in units of execution workload per second. Another unit of throughput is [[instruction per cycle|instructions per cycle]] (IPC) and its reciprocal, [[cycle per instruction|cycles per instruction]] (CPI), is another unit of latency.

Speedup is dimensionless and defined differently for each type of quantity so that it is a consistent metric.

===Speedup in latency===
Speedup in ''latency'' is defined by the following formula:<ref>{{cite book
| last1 = Hennessy
| first1 = John L.
| last2 = David A.
| first2 = Patterson
| title = Computer Architecture: A Quantitive Approach
| url = https://archive.org/details/computerarchitec00henn_754
| url-access = limited
| location = Waltham, MA
| publisher = [[Morgan Kaufmann]]
| pages = [https://archive.org/details/computerarchitec00henn_754/page/n71 46]–47
| date = 2012
| isbn = 978-0-12-383872-8
}}</ref>
: <math>S_\text{latency} = \frac{L_1}{L_2} = \frac{T_1W_2}{T_2W_1},</math>
where
* ''S''<sub>latency</sub> is the speedup in latency of the architecture 2 with respect to the architecture 1;
* ''L''<sub>1</sub> is the latency of the architecture 1;
* ''L''<sub>2</sub> is the latency of the architecture 2.

Speedup in latency can be predicted from [[Amdahl's law]] or [[Gustafson's law]].

===Speedup in throughput===
Speedup in ''throughput'' is defined by the formula:<ref>{{cite book
| last = Baer
| first = Jean-Loup
| title = Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors
| url = https://archive.org/details/microprocessorar00baer_825
| url-access = limited
| location = New York
| publisher = [[Cambridge University Press]]
| pages = [https://archive.org/details/microprocessorar00baer_825/page/n25 10]
| date = 2010
| isbn = 978-0-521-76992-1
}}</ref>
: <math>S_\text{throughput} = \frac{Q_2}{Q_1} = \frac{\rho_2A_2T_1W_2}{\rho_1A_1T_2W_1} = \frac{\rho_2A_2}{\rho_1A_1}S_\text{latency},</math>
where
* ''S''<sub>throughput</sub> is the speedup in throughput of the architecture 2 with respect to the architecture 1;
* ''Q''<sub>1</sub> is the throughput of the architecture 1;
* ''Q''<sub>2</sub> is the throughput of the architecture 2.